Struct esp32s3_hal::pac::spi0::sram_cmd::W

pub struct W(_);

Register SRAM_CMD writer

Implementations

impl W

pub fn sclk_mode(
    &mut self
) -> FieldWriterRaw<'_, u32, SRAM_CMD_SPEC, u8, u8, Unsafe, 2, 0>

Bits 0:1 - SPI_CLK mode bits when SPI0 accesses to Ext_RAM. 0: SPI_CLK is off when CS inactive 1: SPI_CLK is delayed one cycle after CS inactive 2: SPI_CLK is delayed two cycles after CS inactive 3: SPI_CLK is always on.

pub fn swb_mode(
    &mut self
) -> FieldWriterRaw<'_, u32, SRAM_CMD_SPEC, u8, u8, Unsafe, 8, 2>

Bits 2:9 - Mode bits when SPI0 accesses to Ext_RAM.

pub fn sdin_dual(
    &mut self
) -> BitWriterRaw<'_, u32, SRAM_CMD_SPEC, bool, BitM, 10>

Bit 10 - When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in DIN phase.

pub fn sdout_dual(
    &mut self
) -> BitWriterRaw<'_, u32, SRAM_CMD_SPEC, bool, BitM, 11>

Bit 11 - When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in DOUT phase.

pub fn saddr_dual(
    &mut self
) -> BitWriterRaw<'_, u32, SRAM_CMD_SPEC, bool, BitM, 12>

Bit 12 - When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in ADDR phase.

pub fn scmd_dual(
    &mut self
) -> BitWriterRaw<'_, u32, SRAM_CMD_SPEC, bool, BitM, 13>

Bit 13 - When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in CMD phase.

pub fn sdin_quad(
    &mut self
) -> BitWriterRaw<'_, u32, SRAM_CMD_SPEC, bool, BitM, 14>

Bit 14 - When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in DIN phase.

pub fn sdout_quad(
    &mut self
) -> BitWriterRaw<'_, u32, SRAM_CMD_SPEC, bool, BitM, 15>

Bit 15 - When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in DOUT phase.

pub fn saddr_quad(
    &mut self
) -> BitWriterRaw<'_, u32, SRAM_CMD_SPEC, bool, BitM, 16>

Bit 16 - When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in ADDR phase.

pub fn scmd_quad(
    &mut self
) -> BitWriterRaw<'_, u32, SRAM_CMD_SPEC, bool, BitM, 17>

Bit 17 - When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in CMD phase.

pub fn sdin_oct(
    &mut self
) -> BitWriterRaw<'_, u32, SRAM_CMD_SPEC, bool, BitM, 18>

Bit 18 - When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in DIN phase.

pub fn sdout_oct(
    &mut self
) -> BitWriterRaw<'_, u32, SRAM_CMD_SPEC, bool, BitM, 19>

Bit 19 - When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in DOUT phase.

pub fn saddr_oct(
    &mut self
) -> BitWriterRaw<'_, u32, SRAM_CMD_SPEC, bool, BitM, 20>

Bit 20 - When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in ADDR phase.

pub fn scmd_oct(
    &mut self
) -> BitWriterRaw<'_, u32, SRAM_CMD_SPEC, bool, BitM, 21>

Bit 21 - When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in CMD phase.

pub fn sdummy_out(
    &mut self
) -> BitWriterRaw<'_, u32, SRAM_CMD_SPEC, bool, BitM, 22>

Bit 22 - When SPI0 accesses to Ext_RAM, in the DUMMY phase the signal level of SPI bus is output by the SPI0 controller.

pub unsafe fn bits(&mut self, bits: u32) -> &mut W

Writes raw bits to the register.

Methods from Deref<Target = W<SRAM_CMD_SPEC>>

pub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>

Writes raw bits to the register.

Safety

Read datasheet or reference manual to find what values are allowed to pass.

Trait Implementations

impl Deref for W

type Target = W<SRAM_CMD_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &<W as Deref>::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut <W as Deref>::Target

Mutably dereferences the value.

impl From<W<SRAM_CMD_SPEC>> for W

fn from(writer: W<SRAM_CMD_SPEC>) -> W

Converts to this type from the input type.