Struct esp32s3_hal::pac::spi0::spi_smem_ddr::SPI_SMEM_DDR_SPEC

pub struct SPI_SMEM_DDR_SPEC;

SPI0 external RAM DDR mode control register

This register you can read, write_with_zero, reset, write, modify. See API.

For information about available fields see spi_smem_ddr module

Trait Implementations

impl Readable for SPI_SMEM_DDR_SPEC

read() method returns spi_smem_ddr::R reader structure

type Reader = R

Result from a call to read and argument to modify.

impl RegisterSpec for SPI_SMEM_DDR_SPEC

type Ux = u32

Raw register type (u8, u16, u32, …).

impl Resettable for SPI_SMEM_DDR_SPEC

reset() method sets SPI_SMEM_DDR to value 0x3020

const RESET_VALUE: <SPI_SMEM_DDR_SPEC as RegisterSpec>::Ux = {transmute(0x00003020): <esp_hal_common::esp32s3::spi0::spi_smem_ddr::SPI_SMEM_DDR_SPEC as esp_hal_common::esp32s3::generic::RegisterSpec>::Ux}

Reset value of the register.

fn reset_value() -> Self::Ux

Reset value of the register.

impl Writable for SPI_SMEM_DDR_SPEC

write(|w| ..) method takes spi_smem_ddr::W writer structure

type Writer = W

Writer type argument to write, et al.

const ZERO_TO_MODIFY_FIELDS_BITMAP: <SPI_SMEM_DDR_SPEC as RegisterSpec>::Ux = {transmute(0x00000000): <esp_hal_common::esp32s3::spi0::spi_smem_ddr::SPI_SMEM_DDR_SPEC as esp_hal_common::esp32s3::generic::RegisterSpec>::Ux}

Specifies the register bits that are not changed if you pass 1 and are changed if you pass 0

const ONE_TO_MODIFY_FIELDS_BITMAP: <SPI_SMEM_DDR_SPEC as RegisterSpec>::Ux = {transmute(0x00000000): <esp_hal_common::esp32s3::spi0::spi_smem_ddr::SPI_SMEM_DDR_SPEC as esp_hal_common::esp32s3::generic::RegisterSpec>::Ux}

Specifies the register bits that are not changed if you pass 0 and are changed if you pass 1