Struct esp32s3_hal::pac::spi0::ctrl2::W
pub struct W(_);
Expand description
Register CTRL2
writer
Implementations§
§impl W
impl W
pub fn cs_setup_time(
&mut self
) -> FieldWriterRaw<'_, u32, CTRL2_SPEC, u8, u8, Unsafe, 5, 0>
pub fn cs_setup_time(
&mut self
) -> FieldWriterRaw<'_, u32, CTRL2_SPEC, u8, u8, Unsafe, 5, 0>
Bits 0:4 - (cycles-1) of PREP phase by SPI_CLK, which is the SPI_CS setup time. These bits are combined with SPI_MEM_CS_SETUP bit.
pub fn cs_hold_time(
&mut self
) -> FieldWriterRaw<'_, u32, CTRL2_SPEC, u8, u8, Unsafe, 5, 5>
pub fn cs_hold_time(
&mut self
) -> FieldWriterRaw<'_, u32, CTRL2_SPEC, u8, u8, Unsafe, 5, 5>
Bits 5:9 - SPI Bus CS (SPI_CS) signal is delayed to inactive by SPI Bus clock (SPI_CLK), which is the SPI_CS hold time in non-ECC mode. These bits are combined with SPI_MEM_CS_HOLD bit.
pub fn ecc_cs_hold_time(
&mut self
) -> FieldWriterRaw<'_, u32, CTRL2_SPEC, u8, u8, Unsafe, 3, 10>
pub fn ecc_cs_hold_time(
&mut self
) -> FieldWriterRaw<'_, u32, CTRL2_SPEC, u8, u8, Unsafe, 3, 10>
Bits 10:12 - SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI_CS hold cycle in ECC mode when accessed flash.
pub fn ecc_skip_page_corner(
&mut self
) -> BitWriterRaw<'_, u32, CTRL2_SPEC, bool, BitM, 13>
pub fn ecc_skip_page_corner(
&mut self
) -> BitWriterRaw<'_, u32, CTRL2_SPEC, bool, BitM, 13>
Bit 13 - 1: MSPI skips page corner when accesses flash. 0: Not skip page corner when accesses flash.
pub fn ecc_16to18_byte_en(
&mut self
) -> BitWriterRaw<'_, u32, CTRL2_SPEC, bool, BitM, 14>
pub fn ecc_16to18_byte_en(
&mut self
) -> BitWriterRaw<'_, u32, CTRL2_SPEC, bool, BitM, 14>
Bit 14 - Set this bit to enable MSPI ECC 16 bytes data with 2 ECC bytes mode when accesses flash.
pub fn cs_hold_delay(
&mut self
) -> FieldWriterRaw<'_, u32, CTRL2_SPEC, u8, u8, Unsafe, 6, 25>
pub fn cs_hold_delay(
&mut self
) -> FieldWriterRaw<'_, u32, CTRL2_SPEC, u8, u8, Unsafe, 6, 25>
Bits 25:30 - These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.
pub fn sync_reset(
&mut self
) -> BitWriterRaw<'_, u32, CTRL2_SPEC, bool, BitM, 31>
pub fn sync_reset(
&mut self
) -> BitWriterRaw<'_, u32, CTRL2_SPEC, bool, BitM, 31>
Bit 31 - The FSM will be reset.
Methods from Deref<Target = W<CTRL2_SPEC>>§
pub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>
pub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>
Writes raw bits to the register.
Safety
Read datasheet or reference manual to find what values are allowed to pass.