Struct esp32s3_hal::pac::spi0::ctrl2::R

pub struct R(_);

Register CTRL2 reader

Implementations

impl R

pub fn cs_setup_time(&self) -> FieldReaderRaw<u8, u8>

Bits 0:4 - (cycles-1) of PREP phase by SPI_CLK, which is the SPI_CS setup time. These bits are combined with SPI_MEM_CS_SETUP bit.

pub fn cs_hold_time(&self) -> FieldReaderRaw<u8, u8>

Bits 5:9 - SPI Bus CS (SPI_CS) signal is delayed to inactive by SPI Bus clock (SPI_CLK), which is the SPI_CS hold time in non-ECC mode. These bits are combined with SPI_MEM_CS_HOLD bit.

pub fn ecc_cs_hold_time(&self) -> FieldReaderRaw<u8, u8>

Bits 10:12 - SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI_CS hold cycle in ECC mode when accessed flash.

pub fn ecc_skip_page_corner(&self) -> BitReaderRaw<bool>

Bit 13 - 1: MSPI skips page corner when accesses flash. 0: Not skip page corner when accesses flash.

pub fn ecc_16to18_byte_en(&self) -> BitReaderRaw<bool>

Bit 14 - Set this bit to enable MSPI ECC 16 bytes data with 2 ECC bytes mode when accesses flash.

pub fn cs_hold_delay(&self) -> FieldReaderRaw<u8, u8>

Bits 25:30 - These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.

pub fn sync_reset(&self) -> BitReaderRaw<bool>

Bit 31 - The FSM will be reset.

Methods from Deref<Target = R<CTRL2_SPEC>>

pub fn bits(&self) -> <REG as RegisterSpec>::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<CTRL2_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &<R as Deref>::Target

Dereferences the value.

impl From<R<CTRL2_SPEC>> for R

fn from(reader: R<CTRL2_SPEC>) -> R

Converts to this type from the input type.