Struct esp32s3_hal::pac::spi0::ctrl1::R

pub struct R(_);

Register CTRL1 reader

Implementations

impl R

pub fn clk_mode(&self) -> FieldReaderRaw<u8, u8>

Bits 0:1 - SPI Bus clock (SPI_CLK) mode bits. 0: SPI Bus clock (SPI_CLK) is off when CS inactive 1: SPI_CLK is delayed one cycle after SPI_CS inactive 2: SPI_CLK is delayed two cycles after SPI_CS inactive 3: SPI_CLK is always on.

pub fn rxfifo_rst(&self) -> BitReaderRaw<bool>

Bit 30 - SPI0 RX FIFO reset signal. Set this bit and clear it before SPI0 transfer starts.

Methods from Deref<Target = R<CTRL1_SPEC>>

pub fn bits(&self) -> <REG as RegisterSpec>::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<CTRL1_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &<R as Deref>::Target

Dereferences the value.

impl From<R<CTRL1_SPEC>> for R

fn from(reader: R<CTRL1_SPEC>) -> R

Converts to this type from the input type.