Struct esp32s3_hal::pac::spi0::cache_sctrl::W

pub struct W(_);

Register CACHE_SCTRL writer

Implementations

impl W

pub fn cache_usr_scmd_4byte(
    &mut self
) -> BitWriterRaw<'_, u32, CACHE_SCTRL_SPEC, bool, BitM, 0>

Bit 0 - Set this bit to enable SPI0 read Ext_RAM with 32 bits address. The value of SPI_MEM_SRAM_ADDR_BITLEN should be 31.

pub fn usr_sram_dio(
    &mut self
) -> BitWriterRaw<'_, u32, CACHE_SCTRL_SPEC, bool, BitM, 1>

Bit 1 - Set the bit to enable 2-bm in all the phases of SPI0 Ext_RAM transfer.

pub fn usr_sram_qio(
    &mut self
) -> BitWriterRaw<'_, u32, CACHE_SCTRL_SPEC, bool, BitM, 2>

Bit 2 - Set the bit to enable QPI mode in all SPI0 Ext_RAM transfer.

pub fn usr_wr_sram_dummy(
    &mut self
) -> BitWriterRaw<'_, u32, CACHE_SCTRL_SPEC, bool, BitM, 3>

Bit 3 - When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY phase in write operations.

pub fn usr_rd_sram_dummy(
    &mut self
) -> BitWriterRaw<'_, u32, CACHE_SCTRL_SPEC, bool, BitM, 4>

Bit 4 - When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY phase in read operations.

pub fn cache_sram_usr_rcmd(
    &mut self
) -> BitWriterRaw<'_, u32, CACHE_SCTRL_SPEC, bool, BitM, 5>

Bit 5 - 1: The command value of SPI0 read Ext_RAM is SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE. 0: The value is 0x2.

pub fn sram_rdummy_cyclelen(
    &mut self
) -> FieldWriterRaw<'_, u32, CACHE_SCTRL_SPEC, u8, u8, Unsafe, 6, 6>

Bits 6:11 - When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus 1 of DUMMY phase in read data transfer.

pub fn sram_addr_bitlen(
    &mut self
) -> FieldWriterRaw<'_, u32, CACHE_SCTRL_SPEC, u8, u8, Unsafe, 6, 14>

Bits 14:19 - When SPI0 accesses to Ext_RAM, it is the length in bits of ADDR phase. The register value shall be (bit_num-1).

pub fn cache_sram_usr_wcmd(
    &mut self
) -> BitWriterRaw<'_, u32, CACHE_SCTRL_SPEC, bool, BitM, 20>

Bit 20 - 1: The command value of SPI0 write Ext_RAM is SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE. 0: The value is 0x3.

pub fn sram_oct(
    &mut self
) -> BitWriterRaw<'_, u32, CACHE_SCTRL_SPEC, bool, BitM, 21>

Bit 21 - Set the bit to enable OPI mode in all SPI0 Ext_RAM transfer.

pub fn sram_wdummy_cyclelen(
    &mut self
) -> FieldWriterRaw<'_, u32, CACHE_SCTRL_SPEC, u8, u8, Unsafe, 6, 22>

Bits 22:27 - When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus 1 of DUMMY phase in write data transfer.

pub unsafe fn bits(&mut self, bits: u32) -> &mut W

Writes raw bits to the register.

Methods from Deref<Target = W<CACHE_SCTRL_SPEC>>

pub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>

Writes raw bits to the register.

Safety

Read datasheet or reference manual to find what values are allowed to pass.

Trait Implementations

impl Deref for W

type Target = W<CACHE_SCTRL_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &<W as Deref>::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut <W as Deref>::Target

Mutably dereferences the value.

impl From<W<CACHE_SCTRL_SPEC>> for W

fn from(writer: W<CACHE_SCTRL_SPEC>) -> W

Converts to this type from the input type.