Struct esp32s3_hal::pac::spi0::cache_sctrl::R
pub struct R(_);Expand description
Register CACHE_SCTRL reader
Implementations§
§impl R
impl R
pub fn cache_usr_scmd_4byte(&self) -> BitReaderRaw<bool>
pub fn cache_usr_scmd_4byte(&self) -> BitReaderRaw<bool>
Bit 0 - Set this bit to enable SPI0 read Ext_RAM with 32 bits address. The value of SPI_MEM_SRAM_ADDR_BITLEN should be 31.
pub fn usr_sram_dio(&self) -> BitReaderRaw<bool>
pub fn usr_sram_dio(&self) -> BitReaderRaw<bool>
Bit 1 - Set the bit to enable 2-bm in all the phases of SPI0 Ext_RAM transfer.
pub fn usr_sram_qio(&self) -> BitReaderRaw<bool>
pub fn usr_sram_qio(&self) -> BitReaderRaw<bool>
Bit 2 - Set the bit to enable QPI mode in all SPI0 Ext_RAM transfer.
pub fn usr_wr_sram_dummy(&self) -> BitReaderRaw<bool>
pub fn usr_wr_sram_dummy(&self) -> BitReaderRaw<bool>
Bit 3 - When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY phase in write operations.
pub fn usr_rd_sram_dummy(&self) -> BitReaderRaw<bool>
pub fn usr_rd_sram_dummy(&self) -> BitReaderRaw<bool>
Bit 4 - When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY phase in read operations.
pub fn cache_sram_usr_rcmd(&self) -> BitReaderRaw<bool>
pub fn cache_sram_usr_rcmd(&self) -> BitReaderRaw<bool>
Bit 5 - 1: The command value of SPI0 read Ext_RAM is SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE. 0: The value is 0x2.
pub fn sram_rdummy_cyclelen(&self) -> FieldReaderRaw<u8, u8>
pub fn sram_rdummy_cyclelen(&self) -> FieldReaderRaw<u8, u8>
Bits 6:11 - When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus 1 of DUMMY phase in read data transfer.
pub fn sram_addr_bitlen(&self) -> FieldReaderRaw<u8, u8>
pub fn sram_addr_bitlen(&self) -> FieldReaderRaw<u8, u8>
Bits 14:19 - When SPI0 accesses to Ext_RAM, it is the length in bits of ADDR phase. The register value shall be (bit_num-1).
pub fn cache_sram_usr_wcmd(&self) -> BitReaderRaw<bool>
pub fn cache_sram_usr_wcmd(&self) -> BitReaderRaw<bool>
Bit 20 - 1: The command value of SPI0 write Ext_RAM is SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE. 0: The value is 0x3.
pub fn sram_oct(&self) -> BitReaderRaw<bool>
pub fn sram_oct(&self) -> BitReaderRaw<bool>
Bit 21 - Set the bit to enable OPI mode in all SPI0 Ext_RAM transfer.
pub fn sram_wdummy_cyclelen(&self) -> FieldReaderRaw<u8, u8>
pub fn sram_wdummy_cyclelen(&self) -> FieldReaderRaw<u8, u8>
Bits 22:27 - When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus 1 of DUMMY phase in write data transfer.
Methods from Deref<Target = R<CACHE_SCTRL_SPEC>>§
pub fn bits(&self) -> <REG as RegisterSpec>::Ux
pub fn bits(&self) -> <REG as RegisterSpec>::Ux
Reads raw bits from register.