Struct esp32s3_hal::pac::spi0::cache_fctrl::W

pub struct W(_);

Register CACHE_FCTRL writer

Implementations

impl W

pub fn cache_req_en(
    &mut self
) -> BitWriterRaw<'_, u32, CACHE_FCTRL_SPEC, bool, BitM, 0>

Bit 0 - Set this bit to enable Cache’s access and SPI0’s transfer.

pub fn cache_usr_cmd_4byte(
    &mut self
) -> BitWriterRaw<'_, u32, CACHE_FCTRL_SPEC, bool, BitM, 1>

Bit 1 - Set this bit to enable SPI0 read flash with 32 bits address. The value of SPI_MEM_USR_ADDR_BITLEN should be 31.

pub fn cache_flash_usr_cmd(
    &mut self
) -> BitWriterRaw<'_, u32, CACHE_FCTRL_SPEC, bool, BitM, 2>

Bit 2 - 1: The command value of SPI0 reads flash is SPI_MEM_USR_COMMAND_VALUE. 0: Hardware read command value, controlled by SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QUAD, SPI_MEM_FREAD_DUAL and SPI_MEM_FASTRD_MODE bits.

pub fn fdin_dual(
    &mut self
) -> BitWriterRaw<'_, u32, CACHE_FCTRL_SPEC, bool, BitM, 3>

Bit 3 - When SPI0 accesses to flash, set this bit to enable 2-bm in DIN phase.

pub fn fdout_dual(
    &mut self
) -> BitWriterRaw<'_, u32, CACHE_FCTRL_SPEC, bool, BitM, 4>

Bit 4 - When SPI0 accesses to flash, set this bit to enable 2-bm in DOUT phase.

pub fn faddr_dual(
    &mut self
) -> BitWriterRaw<'_, u32, CACHE_FCTRL_SPEC, bool, BitM, 5>

Bit 5 - When SPI0 accesses to flash, set this bit to enable 2-bm in ADDR phase.

pub fn fdin_quad(
    &mut self
) -> BitWriterRaw<'_, u32, CACHE_FCTRL_SPEC, bool, BitM, 6>

Bit 6 - When SPI0 accesses to flash, set this bit to enable 4-bm in DIN phase.

pub fn fdout_quad(
    &mut self
) -> BitWriterRaw<'_, u32, CACHE_FCTRL_SPEC, bool, BitM, 7>

Bit 7 - When SPI0 accesses to flash, set this bit to enable 4-bm in DOUT phase.

pub fn faddr_quad(
    &mut self
) -> BitWriterRaw<'_, u32, CACHE_FCTRL_SPEC, bool, BitM, 8>

Bit 8 - When SPI0 accesses to flash, set this bit to enable 4-bm in ADDR phase.

pub unsafe fn bits(&mut self, bits: u32) -> &mut W

Writes raw bits to the register.

Methods from Deref<Target = W<CACHE_FCTRL_SPEC>>

pub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>

Writes raw bits to the register.

Safety

Read datasheet or reference manual to find what values are allowed to pass.

Trait Implementations

impl Deref for W

type Target = W<CACHE_FCTRL_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &<W as Deref>::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut <W as Deref>::Target

Mutably dereferences the value.

impl From<W<CACHE_FCTRL_SPEC>> for W

fn from(writer: W<CACHE_FCTRL_SPEC>) -> W

Converts to this type from the input type.