Struct esp32s3_hal::pac::sens::sar_hall_ctrl::W
pub struct W(_);
Expand description
Register SAR_HALL_CTRL
writer
Implementations§
§impl W
impl W
pub fn xpd_hall(
&mut self
) -> BitWriterRaw<'_, u32, SAR_HALL_CTRL_SPEC, bool, BitM, 28>
pub fn xpd_hall(
&mut self
) -> BitWriterRaw<'_, u32, SAR_HALL_CTRL_SPEC, bool, BitM, 28>
Bit 28 - Power on hall sensor and connect to VP and VN
pub fn xpd_hall_force(
&mut self
) -> BitWriterRaw<'_, u32, SAR_HALL_CTRL_SPEC, bool, BitM, 29>
pub fn xpd_hall_force(
&mut self
) -> BitWriterRaw<'_, u32, SAR_HALL_CTRL_SPEC, bool, BitM, 29>
Bit 29 - 1: XPD HALL is controlled by SW. 0: XPD HALL is controlled by FSM in ULP-coprocessor
pub fn hall_phase(
&mut self
) -> BitWriterRaw<'_, u32, SAR_HALL_CTRL_SPEC, bool, BitM, 30>
pub fn hall_phase(
&mut self
) -> BitWriterRaw<'_, u32, SAR_HALL_CTRL_SPEC, bool, BitM, 30>
Bit 30 - Reverse phase of hall sensor
pub fn hall_phase_force(
&mut self
) -> BitWriterRaw<'_, u32, SAR_HALL_CTRL_SPEC, bool, BitM, 31>
pub fn hall_phase_force(
&mut self
) -> BitWriterRaw<'_, u32, SAR_HALL_CTRL_SPEC, bool, BitM, 31>
Bit 31 - 1: HALL PHASE is controlled by SW 0: HALL PHASE is controlled by FSM in ULP-coprocessor
Methods from Deref<Target = W<SAR_HALL_CTRL_SPEC>>§
pub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>
pub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>
Writes raw bits to the register.
Safety
Read datasheet or reference manual to find what values are allowed to pass.
Trait Implementations§
§impl From<W<SAR_HALL_CTRL_SPEC>> for W
impl From<W<SAR_HALL_CTRL_SPEC>> for W
§fn from(writer: W<SAR_HALL_CTRL_SPEC>) -> W
fn from(writer: W<SAR_HALL_CTRL_SPEC>) -> W
Converts to this type from the input type.