Struct esp32s3_hal::pac::rtc_cntl::clk_conf::R

pub struct R(_);

Register CLK_CONF reader

Implementations

impl R

pub fn efuse_clk_force_gating(&self) -> BitReaderRaw<bool>

Bit 1 - force efuse clk gating

pub fn efuse_clk_force_nogating(&self) -> BitReaderRaw<bool>

Bit 2 - force efuse clk nogating

pub fn ck8m_div_sel_vld(&self) -> BitReaderRaw<bool>

Bit 3 - used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel, then set vld to actually switch the clk

pub fn ck8m_div(&self) -> FieldReaderRaw<u8, u8>

Bits 4:5 - CK8M_D256_OUT divider. 00: div128, 01: div256, 10: div512, 11: div1024.

pub fn enb_ck8m(&self) -> BitReaderRaw<bool>

Bit 6 - disable CK8M and CK8M_D256_OUT

pub fn enb_ck8m_div(&self) -> BitReaderRaw<bool>

Bit 7 - 1: CK8M_D256_OUT is actually CK8M, 0: CK8M_D256_OUT is CK8M divided by 256

pub fn dig_xtal32k_en(&self) -> BitReaderRaw<bool>

Bit 8 - enable CK_XTAL_32K for digital core (no relationship with RTC core)

pub fn dig_clk8m_d256_en(&self) -> BitReaderRaw<bool>

Bit 9 - enable CK8M_D256_OUT for digital core (no relationship with RTC core)

pub fn dig_clk8m_en(&self) -> BitReaderRaw<bool>

Bit 10 - enable CK8M for digital core (no relationship with RTC core)

pub fn ck8m_div_sel(&self) -> FieldReaderRaw<u8, u8>

Bits 12:14 - divider = reg_ck8m_div_sel + 1

pub fn xtal_force_nogating(&self) -> BitReaderRaw<bool>

Bit 15 - XTAL force no gating during sleep

pub fn ck8m_force_nogating(&self) -> BitReaderRaw<bool>

Bit 16 - CK8M force no gating during sleep

pub fn ck8m_dfreq(&self) -> FieldReaderRaw<u8, u8>

Bits 17:24 - CK8M_DFREQ

pub fn ck8m_force_pd(&self) -> BitReaderRaw<bool>

Bit 25 - CK8M force power down

pub fn ck8m_force_pu(&self) -> BitReaderRaw<bool>

Bit 26 - CK8M force power up

pub fn xtal_global_force_gating(&self) -> BitReaderRaw<bool>

Bit 27 - force global xtal gating

pub fn xtal_global_force_nogating(&self) -> BitReaderRaw<bool>

Bit 28 - force global xtal no gating

pub fn fast_clk_rtc_sel(&self) -> BitReaderRaw<bool>

Bit 29 - fast_clk_rtc sel. 0: XTAL div 4, 1: CK8M

pub fn ana_clk_rtc_sel(&self) -> FieldReaderRaw<u8, u8>

Bits 30:31 - select slow clock

Methods from Deref<Target = R<CLK_CONF_SPEC>>

pub fn bits(&self) -> <REG as RegisterSpec>::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<CLK_CONF_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &<R as Deref>::Target

Dereferences the value.

impl From<R<CLK_CONF_SPEC>> for R

fn from(reader: R<CLK_CONF_SPEC>) -> R

Converts to this type from the input type.