Struct esp32s3_hal::pac::rmt::sys_conf::W
pub struct W(_);
Expand description
Register SYS_CONF
writer
Implementations§
§impl W
impl W
pub fn apb_fifo_mask(
&mut self
) -> BitWriterRaw<'_, u32, SYS_CONF_SPEC, bool, BitM, 0>
pub fn apb_fifo_mask(
&mut self
) -> BitWriterRaw<'_, u32, SYS_CONF_SPEC, bool, BitM, 0>
Bit 0 - 1’h1: access memory directly. 1’h0: access memory by FIFO.
pub fn mem_clk_force_on(
&mut self
) -> BitWriterRaw<'_, u32, SYS_CONF_SPEC, bool, BitM, 1>
pub fn mem_clk_force_on(
&mut self
) -> BitWriterRaw<'_, u32, SYS_CONF_SPEC, bool, BitM, 1>
Bit 1 - Set this bit to enable the clock for RMT memory.
pub fn mem_force_pd(
&mut self
) -> BitWriterRaw<'_, u32, SYS_CONF_SPEC, bool, BitM, 2>
pub fn mem_force_pd(
&mut self
) -> BitWriterRaw<'_, u32, SYS_CONF_SPEC, bool, BitM, 2>
Bit 2 - Set this bit to power down RMT memory.
pub fn mem_force_pu(
&mut self
) -> BitWriterRaw<'_, u32, SYS_CONF_SPEC, bool, BitM, 3>
pub fn mem_force_pu(
&mut self
) -> BitWriterRaw<'_, u32, SYS_CONF_SPEC, bool, BitM, 3>
Bit 3 - 1: Disable RMT memory light sleep power down function. 0: Power down RMT memory when RMT is in light sleep mode.
pub fn sclk_div_num(
&mut self
) -> FieldWriterRaw<'_, u32, SYS_CONF_SPEC, u8, u8, Unsafe, 8, 4>
pub fn sclk_div_num(
&mut self
) -> FieldWriterRaw<'_, u32, SYS_CONF_SPEC, u8, u8, Unsafe, 8, 4>
Bits 4:11 - the integral part of the fractional divisor
pub fn sclk_div_a(
&mut self
) -> FieldWriterRaw<'_, u32, SYS_CONF_SPEC, u8, u8, Unsafe, 6, 12>
pub fn sclk_div_a(
&mut self
) -> FieldWriterRaw<'_, u32, SYS_CONF_SPEC, u8, u8, Unsafe, 6, 12>
Bits 12:17 - the numerator of the fractional part of the fractional divisor
pub fn sclk_div_b(
&mut self
) -> FieldWriterRaw<'_, u32, SYS_CONF_SPEC, u8, u8, Unsafe, 6, 18>
pub fn sclk_div_b(
&mut self
) -> FieldWriterRaw<'_, u32, SYS_CONF_SPEC, u8, u8, Unsafe, 6, 18>
Bits 18:23 - the denominator of the fractional part of the fractional divisor
pub fn sclk_sel(
&mut self
) -> FieldWriterRaw<'_, u32, SYS_CONF_SPEC, u8, u8, Unsafe, 2, 24>
pub fn sclk_sel(
&mut self
) -> FieldWriterRaw<'_, u32, SYS_CONF_SPEC, u8, u8, Unsafe, 2, 24>
Bits 24:25 - choose the clock source of rmt_sclk. 1:CLK_80Mhz;2:CLK_8MHz; 2:XTAL
pub fn sclk_active(
&mut self
) -> BitWriterRaw<'_, u32, SYS_CONF_SPEC, bool, BitM, 26>
pub fn sclk_active(
&mut self
) -> BitWriterRaw<'_, u32, SYS_CONF_SPEC, bool, BitM, 26>
Bit 26 - rmt_sclk switch
pub fn clk_en(&mut self) -> BitWriterRaw<'_, u32, SYS_CONF_SPEC, bool, BitM, 31>
pub fn clk_en(&mut self) -> BitWriterRaw<'_, u32, SYS_CONF_SPEC, bool, BitM, 31>
Bit 31 - RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: Power down the drive clock of registers
Methods from Deref<Target = W<SYS_CONF_SPEC>>§
pub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>
pub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>
Writes raw bits to the register.
Safety
Read datasheet or reference manual to find what values are allowed to pass.