Struct esp32s3_hal::pac::pwm0::int_clr::W

pub struct W(_);
Expand description

Register INT_CLR writer

Implementations§

Bit 0 - Set this bit to clear the interrupt triggered when the timer 0 stops.

Bit 1 - Set this bit to clear the interrupt triggered when the timer 1 stops.

Bit 2 - Set this bit to clear the interrupt triggered when the timer 2 stops.

Bit 3 - Set this bit to clear the interrupt triggered by a PWM timer 0 TEZ event.

Bit 4 - Set this bit to clear the interrupt triggered by a PWM timer 1 TEZ event.

Bit 5 - Set this bit to clear the interrupt triggered by a PWM timer 2 TEZ event.

Bit 6 - Set this bit to clear the interrupt triggered by a PWM timer 0 TEP event.

Bit 7 - Set this bit to clear the interrupt triggered by a PWM timer 1 TEP event.

Bit 8 - Set this bit to clear the interrupt triggered by a PWM timer 2 TEP event.

Bit 9 - Set this bit to clear the interrupt triggered when event_f0 starts.

Bit 10 - Set this bit to clear the interrupt triggered when event_f1 starts.

Bit 11 - Set this bit to clear the interrupt triggered when event_f2 starts.

Bit 12 - Set this bit to clear the interrupt triggered when event_f0 ends.

Bit 13 - Set this bit to clear the interrupt triggered when event_f1 ends.

Bit 14 - Set this bit to clear the interrupt triggered when event_f2 ends.

Bit 15 - Set this bit to clear the interrupt triggered by a PWM operator 0 TEA event

Bit 16 - Set this bit to clear the interrupt triggered by a PWM operator 1 TEA event

Bit 17 - Set this bit to clear the interrupt triggered by a PWM operator 2 TEA event

Bit 18 - Set this bit to clear the interrupt triggered by a PWM operator 0 TEB event

Bit 19 - Set this bit to clear the interrupt triggered by a PWM operator 1 TEB event

Bit 20 - Set this bit to clear the interrupt triggered by a PWM operator 2 TEB event

Bit 21 - Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM0.

Bit 22 - Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM1.

Bit 23 - Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM2.

Bit 24 - Set this bit to clear the interrupt triggered by a one-shot mode action on PWM0.

Bit 25 - Set this bit to clear the interrupt triggered by a one-shot mode action on PWM1.

Bit 26 - Set this bit to clear the interrupt triggered by a one-shot mode action on PWM2.

Bit 27 - Set this bit to clear the interrupt triggered by capture on channel 0.

Bit 28 - Set this bit to clear the interrupt triggered by capture on channel 1.

Bit 29 - Set this bit to clear the interrupt triggered by capture on channel 2.

Writes raw bits to the register.

Methods from Deref<Target = W<INT_CLR_SPEC>>§

Writes raw bits to the register.

Safety

Read datasheet or reference manual to find what values are allowed to pass.

Trait Implementations§

The resulting type after dereferencing.
Dereferences the value.
Mutably dereferences the value.
Converts to this type from the input type.

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The type returned in the event of a conversion error.
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The type returned in the event of a conversion error.
Performs the conversion.