Struct esp32s3_hal::pac::pwm0::db1_cfg::R

pub struct R(_);

Register DB1_CFG reader

Implementations

impl R

pub fn db1_fed_upmethod(&self) -> FieldReaderRaw<u8, u8>

Bits 0:3 - Update method for FED (falling edge delay) active register. 0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze

pub fn db1_red_upmethod(&self) -> FieldReaderRaw<u8, u8>

Bits 4:7 - Update method for RED (rising edge delay) active register. 0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze

pub fn db1_deb_mode(&self) -> BitReaderRaw<bool>

Bit 8 - S8 in documentation, dual-edge B mode, 0: fed/red take effect on different path separately, 1: fed/red take effect on B path, A out is in bypass or dulpB mode

pub fn db1_a_outswap(&self) -> BitReaderRaw<bool>

Bit 9 - S6 in documentation

pub fn db1_b_outswap(&self) -> BitReaderRaw<bool>

Bit 10 - S7 in documentation

pub fn db1_red_insel(&self) -> BitReaderRaw<bool>

Bit 11 - S4 in documentation

pub fn db1_fed_insel(&self) -> BitReaderRaw<bool>

Bit 12 - S5 in documentation

pub fn db1_red_outinvert(&self) -> BitReaderRaw<bool>

Bit 13 - S2 in documentation

pub fn db1_fed_outinvert(&self) -> BitReaderRaw<bool>

Bit 14 - S3 in documentation

pub fn db1_a_outbypass(&self) -> BitReaderRaw<bool>

Bit 15 - S1 in documentation

pub fn db1_b_outbypass(&self) -> BitReaderRaw<bool>

Bit 16 - S0 in documentation

pub fn db1_clk_sel(&self) -> BitReaderRaw<bool>

Bit 17 - Dead time generator 1 clock selection. 0: PWM_clk, 1: PT_clk

Methods from Deref<Target = R<DB1_CFG_SPEC>>

pub fn bits(&self) -> <REG as RegisterSpec>::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<DB1_CFG_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &<R as Deref>::Target

Dereferences the value.

impl From<R<DB1_CFG_SPEC>> for R

fn from(reader: R<DB1_CFG_SPEC>) -> R

Converts to this type from the input type.