Struct esp32s3_hal::pac::pwm0::cap_timer_cfg::W
pub struct W(_);
Expand description
Register CAP_TIMER_CFG
writer
Implementations§
§impl W
impl W
pub fn cap_timer_en(
&mut self
) -> BitWriterRaw<'_, u32, CAP_TIMER_CFG_SPEC, bool, BitM, 0>
pub fn cap_timer_en(
&mut self
) -> BitWriterRaw<'_, u32, CAP_TIMER_CFG_SPEC, bool, BitM, 0>
Bit 0 - When set, capture timer incrementing under APB_clk is enabled.
pub fn cap_synci_en(
&mut self
) -> BitWriterRaw<'_, u32, CAP_TIMER_CFG_SPEC, bool, BitM, 1>
pub fn cap_synci_en(
&mut self
) -> BitWriterRaw<'_, u32, CAP_TIMER_CFG_SPEC, bool, BitM, 1>
Bit 1 - When set, capture timer sync is enabled.
pub fn cap_synci_sel(
&mut self
) -> FieldWriterRaw<'_, u32, CAP_TIMER_CFG_SPEC, u8, u8, Unsafe, 3, 2>
pub fn cap_synci_sel(
&mut self
) -> FieldWriterRaw<'_, u32, CAP_TIMER_CFG_SPEC, u8, u8, Unsafe, 3, 2>
Bits 2:4 - capture module sync input selection. 0: none, 1: timer0 sync_out, 2: timer1 sync_out, 3: timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix
pub fn cap_sync_sw(
&mut self
) -> BitWriterRaw<'_, u32, CAP_TIMER_CFG_SPEC, bool, BitM, 5>
pub fn cap_sync_sw(
&mut self
) -> BitWriterRaw<'_, u32, CAP_TIMER_CFG_SPEC, bool, BitM, 5>
Bit 5 - Write 1 will force a capture timer sync, capture timer is loaded with value in phase register.
Methods from Deref<Target = W<CAP_TIMER_CFG_SPEC>>§
pub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>
pub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>
Writes raw bits to the register.
Safety
Read datasheet or reference manual to find what values are allowed to pass.
Trait Implementations§
§impl From<W<CAP_TIMER_CFG_SPEC>> for W
impl From<W<CAP_TIMER_CFG_SPEC>> for W
§fn from(writer: W<CAP_TIMER_CFG_SPEC>) -> W
fn from(writer: W<CAP_TIMER_CFG_SPEC>) -> W
Converts to this type from the input type.