Struct esp32s3_hal::pac::pcnt::u_conf0::R

pub struct R(_);

Expand description

Register U%s_CONF0 reader

Implementations§

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impl R

pub fn filter_thres_u(&self) -> FieldReaderRaw<u16, u16>

Bits 0:9 - This sets the maximum threshold, in APB_CLK cycles, for the filter. Any pulses with width less than this will be ignored when the filter is enabled.

pub fn filter_en_u(&self) -> BitReaderRaw<bool>

Bit 10 - This is the enable bit for unit %s’s input filter.

pub fn thr_zero_en_u(&self) -> BitReaderRaw<bool>

Bit 11 - This is the enable bit for unit %s’s zero comparator.

pub fn thr_h_lim_en_u(&self) -> BitReaderRaw<bool>

Bit 12 - This is the enable bit for unit %s’s thr_h_lim comparator.

pub fn thr_l_lim_en_u(&self) -> BitReaderRaw<bool>

Bit 13 - This is the enable bit for unit %s’s thr_l_lim comparator.

pub fn thr_thres0_en_u(&self) -> BitReaderRaw<bool>

Bit 14 - This is the enable bit for unit %s’s thres0 comparator.

pub fn thr_thres1_en_u(&self) -> BitReaderRaw<bool>

Bit 15 - This is the enable bit for unit %s’s thres1 comparator.

pub fn ch0_neg_mode_u(&self) -> FieldReaderRaw<u8, u8>

Bits 16:17 - This register sets the behavior when the signal input of channel 0 detects a negative edge. 1: Increase the counter;2: Decrease the counter;0, 3: No effect on counter

pub fn ch0_pos_mode_u(&self) -> FieldReaderRaw<u8, u8>

Bits 18:19 - This register sets the behavior when the signal input of channel 0 detects a positive edge. 1: Increase the counter;2: Decrease the counter;0, 3: No effect on counter

pub fn ch0_hctrl_mode_u(&self) -> FieldReaderRaw<u8, u8>

Bits 20:21 - This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high. 0: No modification;1: Invert behavior (increase -> decrease, decrease -> increase);2, 3: Inhibit counter modification

pub fn ch0_lctrl_mode_u(&self) -> FieldReaderRaw<u8, u8>

Bits 22:23 - This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low. 0: No modification;1: Invert behavior (increase -> decrease, decrease -> increase);2, 3: Inhibit counter modification

pub fn ch1_neg_mode_u(&self) -> FieldReaderRaw<u8, u8>

Bits 24:25 - This register sets the behavior when the signal input of channel 1 detects a negative edge. 1: Increment the counter;2: Decrement the counter;0, 3: No effect on counter

pub fn ch1_pos_mode_u(&self) -> FieldReaderRaw<u8, u8>

Bits 26:27 - This register sets the behavior when the signal input of channel 1 detects a positive edge. 1: Increment the counter;2: Decrement the counter;0, 3: No effect on counter

pub fn ch1_hctrl_mode_u(&self) -> FieldReaderRaw<u8, u8>

Bits 28:29 - This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high. 0: No modification;1: Invert behavior (increase -> decrease, decrease -> increase);2, 3: Inhibit counter modification

pub fn ch1_lctrl_mode_u(&self) -> FieldReaderRaw<u8, u8>

Bits 30:31 - This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low. 0: No modification;1: Invert behavior (increase -> decrease, decrease -> increase);2, 3: Inhibit counter modification