Struct esp32s3_hal::pac::lcd_cam::lcd_data_dout_mode::R

pub struct R(_);

Expand description

Register LCD_DATA_DOUT_MODE reader

Implementations§

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impl R

pub fn dout0_mode(&self) -> FieldReaderRaw<u8, u8>

Bits 0:1 - The output data bit 0 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.

pub fn dout1_mode(&self) -> FieldReaderRaw<u8, u8>

Bits 2:3 - The output data bit 2 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.

pub fn dout2_mode(&self) -> FieldReaderRaw<u8, u8>

Bits 4:5 - The output data bit 4 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.

pub fn dout3_mode(&self) -> FieldReaderRaw<u8, u8>

Bits 6:7 - The output data bit 6 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.

pub fn dout4_mode(&self) -> FieldReaderRaw<u8, u8>

Bits 8:9 - The output data bit 8 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.

pub fn dout5_mode(&self) -> FieldReaderRaw<u8, u8>

Bits 10:11 - The output data bit 10 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.

pub fn dout6_mode(&self) -> FieldReaderRaw<u8, u8>

Bits 12:13 - The output data bit 12 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.

pub fn dout7_mode(&self) -> FieldReaderRaw<u8, u8>

Bits 14:15 - The output data bit 14 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.

pub fn dout8_mode(&self) -> FieldReaderRaw<u8, u8>

Bits 16:17 - The output data bit 16 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.

pub fn dout9_mode(&self) -> FieldReaderRaw<u8, u8>

Bits 18:19 - The output data bit 18 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.

pub fn dout10_mode(&self) -> FieldReaderRaw<u8, u8>

Bits 20:21 - The output data bit 20 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.

pub fn dout11_mode(&self) -> FieldReaderRaw<u8, u8>

Bits 22:23 - The output data bit 22 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.

pub fn dout12_mode(&self) -> FieldReaderRaw<u8, u8>

Bits 24:25 - The output data bit 24 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.

pub fn dout13_mode(&self) -> FieldReaderRaw<u8, u8>

Bits 26:27 - The output data bit 26 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.

pub fn dout14_mode(&self) -> FieldReaderRaw<u8, u8>

Bits 28:29 - The output data bit 28 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.

pub fn dout15_mode(&self) -> FieldReaderRaw<u8, u8>

Bits 30:31 - The output data bit 30 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.