Struct esp32s3_hal::pac::lcd_cam::lcd_clock::W
pub struct W(_);
Expand description
Register LCD_CLOCK
writer
Implementations§
§impl W
impl W
pub fn lcd_clkcnt_n(
&mut self
) -> FieldWriterRaw<'_, u32, LCD_CLOCK_SPEC, u8, u8, Unsafe, 6, 0>
pub fn lcd_clkcnt_n(
&mut self
) -> FieldWriterRaw<'_, u32, LCD_CLOCK_SPEC, u8, u8, Unsafe, 6, 0>
Bits 0:5 - f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0.
pub fn lcd_clk_equ_sysclk(
&mut self
) -> BitWriterRaw<'_, u32, LCD_CLOCK_SPEC, bool, BitM, 6>
pub fn lcd_clk_equ_sysclk(
&mut self
) -> BitWriterRaw<'_, u32, LCD_CLOCK_SPEC, bool, BitM, 6>
Bit 6 - 1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1).
pub fn lcd_ck_idle_edge(
&mut self
) -> BitWriterRaw<'_, u32, LCD_CLOCK_SPEC, bool, BitM, 7>
pub fn lcd_ck_idle_edge(
&mut self
) -> BitWriterRaw<'_, u32, LCD_CLOCK_SPEC, bool, BitM, 7>
Bit 7 - 1: LCD_PCLK line is high when idle 0: LCD_PCLK line is low when idle.
pub fn lcd_ck_out_edge(
&mut self
) -> BitWriterRaw<'_, u32, LCD_CLOCK_SPEC, bool, BitM, 8>
pub fn lcd_ck_out_edge(
&mut self
) -> BitWriterRaw<'_, u32, LCD_CLOCK_SPEC, bool, BitM, 8>
Bit 8 - 1: LCD_PCLK high in first half clock cycle. 0: LCD_PCLK low in first half clock cycle.
pub fn lcd_clkm_div_num(
&mut self
) -> FieldWriterRaw<'_, u32, LCD_CLOCK_SPEC, u8, u8, Unsafe, 8, 9>
pub fn lcd_clkm_div_num(
&mut self
) -> FieldWriterRaw<'_, u32, LCD_CLOCK_SPEC, u8, u8, Unsafe, 8, 9>
Bits 9:16 - Integral LCD clock divider value
pub fn lcd_clkm_div_b(
&mut self
) -> FieldWriterRaw<'_, u32, LCD_CLOCK_SPEC, u8, u8, Unsafe, 6, 17>
pub fn lcd_clkm_div_b(
&mut self
) -> FieldWriterRaw<'_, u32, LCD_CLOCK_SPEC, u8, u8, Unsafe, 6, 17>
Bits 17:22 - Fractional clock divider numerator value
pub fn lcd_clkm_div_a(
&mut self
) -> FieldWriterRaw<'_, u32, LCD_CLOCK_SPEC, u8, u8, Unsafe, 6, 23>
pub fn lcd_clkm_div_a(
&mut self
) -> FieldWriterRaw<'_, u32, LCD_CLOCK_SPEC, u8, u8, Unsafe, 6, 23>
Bits 23:28 - Fractional clock divider denominator value
pub fn lcd_clk_sel(
&mut self
) -> FieldWriterRaw<'_, u32, LCD_CLOCK_SPEC, u8, u8, Unsafe, 2, 29>
pub fn lcd_clk_sel(
&mut self
) -> FieldWriterRaw<'_, u32, LCD_CLOCK_SPEC, u8, u8, Unsafe, 2, 29>
Bits 29:30 - Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock.
pub fn clk_en(
&mut self
) -> BitWriterRaw<'_, u32, LCD_CLOCK_SPEC, bool, BitM, 31>
pub fn clk_en(
&mut self
) -> BitWriterRaw<'_, u32, LCD_CLOCK_SPEC, bool, BitM, 31>
Bit 31 - Set this bit to enable clk gate
Methods from Deref<Target = W<LCD_CLOCK_SPEC>>§
pub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>
pub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>
Writes raw bits to the register.
Safety
Read datasheet or reference manual to find what values are allowed to pass.