Struct esp32s3_hal::pac::i2s1::tx_conf::R
pub struct R(_);Expand description
Register TX_CONF reader
Implementations§
§impl R
impl R
pub fn tx_slave_mod(&self) -> BitReaderRaw<bool>
pub fn tx_slave_mod(&self) -> BitReaderRaw<bool>
Bit 3 - Set this bit to enable slave transmitter mode
pub fn tx_chan_equal(&self) -> BitReaderRaw<bool>
pub fn tx_chan_equal(&self) -> BitReaderRaw<bool>
Bit 6 - 1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.
pub fn tx_big_endian(&self) -> BitReaderRaw<bool>
pub fn tx_big_endian(&self) -> BitReaderRaw<bool>
Bit 7 - I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.
pub fn tx_update(&self) -> BitReaderRaw<bool>
pub fn tx_update(&self) -> BitReaderRaw<bool>
Bit 8 - Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done.
pub fn tx_mono_fst_vld(&self) -> BitReaderRaw<bool>
pub fn tx_mono_fst_vld(&self) -> BitReaderRaw<bool>
Bit 9 - 1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode.
pub fn tx_pcm_conf(&self) -> FieldReaderRaw<u8, u8>
pub fn tx_pcm_conf(&self) -> FieldReaderRaw<u8, u8>
Bits 10:11 - I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
pub fn tx_pcm_bypass(&self) -> BitReaderRaw<bool>
pub fn tx_pcm_bypass(&self) -> BitReaderRaw<bool>
Bit 12 - Set this bit to bypass Compress/Decompress module for transmitted data.
pub fn tx_stop_en(&self) -> BitReaderRaw<bool>
pub fn tx_stop_en(&self) -> BitReaderRaw<bool>
Bit 13 - Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy
pub fn tx_left_align(&self) -> BitReaderRaw<bool>
pub fn tx_left_align(&self) -> BitReaderRaw<bool>
Bit 15 - 1: I2S TX left alignment mode. 0: I2S TX right alignment mode.
pub fn tx_24_fill_en(&self) -> BitReaderRaw<bool>
pub fn tx_24_fill_en(&self) -> BitReaderRaw<bool>
Bit 16 - 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode
pub fn tx_ws_idle_pol(&self) -> BitReaderRaw<bool>
pub fn tx_ws_idle_pol(&self) -> BitReaderRaw<bool>
Bit 17 - 0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: WS should be 1 when sending left channel data, and WS is 0in right channel.
pub fn tx_bit_order(&self) -> BitReaderRaw<bool>
pub fn tx_bit_order(&self) -> BitReaderRaw<bool>
Bit 18 - I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first.
pub fn tx_chan_mod(&self) -> FieldReaderRaw<u8, u8>
pub fn tx_chan_mod(&self) -> FieldReaderRaw<u8, u8>
Bits 24:26 - I2S transmitter channel mode configuration bits.
pub fn sig_loopback(&self) -> BitReaderRaw<bool>
pub fn sig_loopback(&self) -> BitReaderRaw<bool>
Bit 27 - Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals.
Methods from Deref<Target = R<TX_CONF_SPEC>>§
pub fn bits(&self) -> <REG as RegisterSpec>::Ux
pub fn bits(&self) -> <REG as RegisterSpec>::Ux
Reads raw bits from register.