Struct esp32s3_hal::pac::extmem::icache_ctrl::W

pub struct W(_);

Register ICACHE_CTRL writer

Implementations

impl W

pub fn icache_enable(
    &mut self
) -> BitWriterRaw<'_, u32, ICACHE_CTRL_SPEC, bool, BitM, 0>

Bit 0 - The bit is used to activate the data cache. 0: disable, 1: enable

pub fn icache_way_mode(
    &mut self
) -> BitWriterRaw<'_, u32, ICACHE_CTRL_SPEC, bool, BitM, 1>

Bit 1 - The bit is used to configure cache way mode.0: 4-way, 1: 8-way

pub fn icache_size_mode(
    &mut self
) -> BitWriterRaw<'_, u32, ICACHE_CTRL_SPEC, bool, BitM, 2>

Bit 2 - The bit is used to configure cache memory size.0: 16KB, 1: 32KB

pub fn icache_blocksize_mode(
    &mut self
) -> BitWriterRaw<'_, u32, ICACHE_CTRL_SPEC, bool, BitM, 3>

Bit 3 - The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes

pub unsafe fn bits(&mut self, bits: u32) -> &mut W

Writes raw bits to the register.

Methods from Deref<Target = W<ICACHE_CTRL_SPEC>>

pub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>

Writes raw bits to the register.

Safety

Read datasheet or reference manual to find what values are allowed to pass.

Trait Implementations

impl Deref for W

type Target = W<ICACHE_CTRL_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &<W as Deref>::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut <W as Deref>::Target

Mutably dereferences the value.

impl From<W<ICACHE_CTRL_SPEC>> for W

fn from(writer: W<ICACHE_CTRL_SPEC>) -> W

Converts to this type from the input type.