Struct esp32s3_hal::pac::extmem::dcache_ctrl1::W

pub struct W(_);

Register DCACHE_CTRL1 writer

Implementations

impl W

pub fn dcache_shut_core0_bus(
    &mut self
) -> BitWriterRaw<'_, u32, DCACHE_CTRL1_SPEC, bool, BitM, 0>

Bit 0 - The bit is used to disable core0 dbus, 0: enable, 1: disable

pub fn dcache_shut_core1_bus(
    &mut self
) -> BitWriterRaw<'_, u32, DCACHE_CTRL1_SPEC, bool, BitM, 1>

Bit 1 - The bit is used to disable core1 dbus, 0: enable, 1: disable

pub unsafe fn bits(&mut self, bits: u32) -> &mut W

Writes raw bits to the register.

Methods from Deref<Target = W<DCACHE_CTRL1_SPEC>>

pub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>

Writes raw bits to the register.

Safety

Read datasheet or reference manual to find what values are allowed to pass.

Trait Implementations

impl Deref for W

type Target = W<DCACHE_CTRL1_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &<W as Deref>::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut <W as Deref>::Target

Mutably dereferences the value.

impl From<W<DCACHE_CTRL1_SPEC>> for W

fn from(writer: W<DCACHE_CTRL1_SPEC>) -> W

Converts to this type from the input type.