Struct esp32s3_hal::pac::extmem::cache_ilg_int_ena::R

pub struct R(_);

Register CACHE_ILG_INT_ENA reader

Implementations

impl R

pub fn icache_sync_op_fault_int_ena(&self) -> BitReaderRaw<bool>

Bit 0 - The bit is used to enable interrupt by sync configurations fault.

pub fn icache_preload_op_fault_int_ena(&self) -> BitReaderRaw<bool>

Bit 1 - The bit is used to enable interrupt by preload configurations fault.

pub fn dcache_sync_op_fault_int_ena(&self) -> BitReaderRaw<bool>

Bit 2 - The bit is used to enable interrupt by sync configurations fault.

pub fn dcache_preload_op_fault_int_ena(&self) -> BitReaderRaw<bool>

Bit 3 - The bit is used to enable interrupt by preload configurations fault.

pub fn dcache_write_flash_int_ena(&self) -> BitReaderRaw<bool>

Bit 4 - The bit is used to enable interrupt by dcache trying to write flash.

pub fn mmu_entry_fault_int_ena(&self) -> BitReaderRaw<bool>

Bit 5 - The bit is used to enable interrupt by mmu entry fault.

pub fn dcache_occupy_exc_int_ena(&self) -> BitReaderRaw<bool>

Bit 6 - The bit is used to enable interrupt by dcache trying to replace a line whose blocks all have been occupied by occupy-mode.

pub fn ibus_cnt_ovf_int_ena(&self) -> BitReaderRaw<bool>

Bit 7 - The bit is used to enable interrupt by ibus counter overflow.

pub fn dbus_cnt_ovf_int_ena(&self) -> BitReaderRaw<bool>

Bit 8 - The bit is used to enable interrupt by dbus counter overflow.

Methods from Deref<Target = R<CACHE_ILG_INT_ENA_SPEC>>

pub fn bits(&self) -> <REG as RegisterSpec>::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<CACHE_ILG_INT_ENA_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &<R as Deref>::Target

Dereferences the value.

impl From<R<CACHE_ILG_INT_ENA_SPEC>> for R

fn from(reader: R<CACHE_ILG_INT_ENA_SPEC>) -> R

Converts to this type from the input type.