Struct esp32s3_hal::pac::extmem::cache_ilg_int_clr::W
pub struct W(_);
Expand description
Register CACHE_ILG_INT_CLR
writer
Implementations§
§impl W
impl W
pub fn icache_sync_op_fault_int_clr(
&mut self
) -> BitWriterRaw<'_, u32, CACHE_ILG_INT_CLR_SPEC, bool, BitM, 0>
pub fn icache_sync_op_fault_int_clr(
&mut self
) -> BitWriterRaw<'_, u32, CACHE_ILG_INT_CLR_SPEC, bool, BitM, 0>
Bit 0 - The bit is used to clear interrupt by sync configurations fault.
pub fn icache_preload_op_fault_int_clr(
&mut self
) -> BitWriterRaw<'_, u32, CACHE_ILG_INT_CLR_SPEC, bool, BitM, 1>
pub fn icache_preload_op_fault_int_clr(
&mut self
) -> BitWriterRaw<'_, u32, CACHE_ILG_INT_CLR_SPEC, bool, BitM, 1>
Bit 1 - The bit is used to clear interrupt by preload configurations fault.
pub fn dcache_sync_op_fault_int_clr(
&mut self
) -> BitWriterRaw<'_, u32, CACHE_ILG_INT_CLR_SPEC, bool, BitM, 2>
pub fn dcache_sync_op_fault_int_clr(
&mut self
) -> BitWriterRaw<'_, u32, CACHE_ILG_INT_CLR_SPEC, bool, BitM, 2>
Bit 2 - The bit is used to clear interrupt by sync configurations fault.
pub fn dcache_preload_op_fault_int_clr(
&mut self
) -> BitWriterRaw<'_, u32, CACHE_ILG_INT_CLR_SPEC, bool, BitM, 3>
pub fn dcache_preload_op_fault_int_clr(
&mut self
) -> BitWriterRaw<'_, u32, CACHE_ILG_INT_CLR_SPEC, bool, BitM, 3>
Bit 3 - The bit is used to clear interrupt by preload configurations fault.
pub fn dcache_write_flash_int_clr(
&mut self
) -> BitWriterRaw<'_, u32, CACHE_ILG_INT_CLR_SPEC, bool, BitM, 4>
pub fn dcache_write_flash_int_clr(
&mut self
) -> BitWriterRaw<'_, u32, CACHE_ILG_INT_CLR_SPEC, bool, BitM, 4>
Bit 4 - The bit is used to clear interrupt by dcache trying to write flash.
pub fn mmu_entry_fault_int_clr(
&mut self
) -> BitWriterRaw<'_, u32, CACHE_ILG_INT_CLR_SPEC, bool, BitM, 5>
pub fn mmu_entry_fault_int_clr(
&mut self
) -> BitWriterRaw<'_, u32, CACHE_ILG_INT_CLR_SPEC, bool, BitM, 5>
Bit 5 - The bit is used to clear interrupt by mmu entry fault.
pub fn dcache_occupy_exc_int_clr(
&mut self
) -> BitWriterRaw<'_, u32, CACHE_ILG_INT_CLR_SPEC, bool, BitM, 6>
pub fn dcache_occupy_exc_int_clr(
&mut self
) -> BitWriterRaw<'_, u32, CACHE_ILG_INT_CLR_SPEC, bool, BitM, 6>
Bit 6 - The bit is used to clear interrupt by dcache trying to replace a line whose blocks all have been occupied by occupy-mode.
pub fn ibus_cnt_ovf_int_clr(
&mut self
) -> BitWriterRaw<'_, u32, CACHE_ILG_INT_CLR_SPEC, bool, BitM, 7>
pub fn ibus_cnt_ovf_int_clr(
&mut self
) -> BitWriterRaw<'_, u32, CACHE_ILG_INT_CLR_SPEC, bool, BitM, 7>
Bit 7 - The bit is used to clear interrupt by ibus counter overflow.
pub fn dbus_cnt_ovf_int_clr(
&mut self
) -> BitWriterRaw<'_, u32, CACHE_ILG_INT_CLR_SPEC, bool, BitM, 8>
pub fn dbus_cnt_ovf_int_clr(
&mut self
) -> BitWriterRaw<'_, u32, CACHE_ILG_INT_CLR_SPEC, bool, BitM, 8>
Bit 8 - The bit is used to clear interrupt by dbus counter overflow.
Methods from Deref<Target = W<CACHE_ILG_INT_CLR_SPEC>>§
pub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>
pub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>
Writes raw bits to the register.
Safety
Read datasheet or reference manual to find what values are allowed to pass.