Struct esp32s3_hal::peripherals::DMA

pub struct DMA { /* private fields */ }

Implementations

impl DMA

pub unsafe fn steal() -> DMA

Unsafely create an instance of this peripheral out of thin air.

Safety

You must ensure that you’re only using one instance of this type at a time.

pub const PTR: *const <DMA as Deref>::Target = {0x6003f000 as *const <esp32s3::DMA as core::ops::Deref>::Target}

Pointer to the register block

pub const fn ptr() -> *const <DMA as Deref>::Target

Return the pointer to the register block

Methods from Deref<Target = RegisterBlock>

pub fn in_conf0_ch(&self, n: usize) -> &Reg<IN_CONF0_CH_SPEC>

0x00..0x14 - Configure 0 register of Rx channel 0

pub fn in_conf0_ch_iter(&self) -> impl Iterator<Item = &Reg<IN_CONF0_CH_SPEC>>

Iterator for array of: 0x00..0x14 - Configure 0 register of Rx channel 0

pub fn in_conf1_ch(&self, n: usize) -> &Reg<IN_CONF1_CH_SPEC>

0x04..0x18 - Configure 1 register of Rx channel 0

pub fn in_conf1_ch_iter(&self) -> impl Iterator<Item = &Reg<IN_CONF1_CH_SPEC>>

Iterator for array of: 0x04..0x18 - Configure 1 register of Rx channel 0

pub fn in_int_raw_ch(&self, n: usize) -> &Reg<IN_INT_RAW_CH_SPEC>

0x08..0x1c - Raw status interrupt of Rx channel 0

pub fn in_int_raw_ch_iter( &self ) -> impl Iterator<Item = &Reg<IN_INT_RAW_CH_SPEC>>

Iterator for array of: 0x08..0x1c - Raw status interrupt of Rx channel 0

pub fn in_int_st_ch(&self, n: usize) -> &Reg<IN_INT_ST_CH_SPEC>

0x0c..0x20 - Masked interrupt of Rx channel 0

pub fn in_int_st_ch_iter(&self) -> impl Iterator<Item = &Reg<IN_INT_ST_CH_SPEC>>

Iterator for array of: 0x0c..0x20 - Masked interrupt of Rx channel 0

pub fn in_int_ena_ch(&self, n: usize) -> &Reg<IN_INT_ENA_CH_SPEC>

0x10..0x24 - Interrupt enable bits of Rx channel 0

pub fn in_int_ena_ch_iter( &self ) -> impl Iterator<Item = &Reg<IN_INT_ENA_CH_SPEC>>

Iterator for array of: 0x10..0x24 - Interrupt enable bits of Rx channel 0

pub fn in_int_clr_ch(&self, n: usize) -> &Reg<IN_INT_CLR_CH_SPEC>

0x14..0x28 - Interrupt clear bits of Rx channel 0

pub fn in_int_clr_ch_iter( &self ) -> impl Iterator<Item = &Reg<IN_INT_CLR_CH_SPEC>>

Iterator for array of: 0x14..0x28 - Interrupt clear bits of Rx channel 0

pub fn infifo_status_ch(&self, n: usize) -> &Reg<INFIFO_STATUS_CH_SPEC>

0x18..0x2c - Receive FIFO status of Rx channel 0

pub fn infifo_status_ch_iter( &self ) -> impl Iterator<Item = &Reg<INFIFO_STATUS_CH_SPEC>>

Iterator for array of: 0x18..0x2c - Receive FIFO status of Rx channel 0

pub fn in_pop_ch(&self, n: usize) -> &Reg<IN_POP_CH_SPEC>

0x1c..0x30 - Pop control register of Rx channel 0

pub fn in_pop_ch_iter(&self) -> impl Iterator<Item = &Reg<IN_POP_CH_SPEC>>

Iterator for array of: 0x1c..0x30 - Pop control register of Rx channel 0

pub fn in_link_ch(&self, n: usize) -> &Reg<IN_LINK_CH_SPEC>

0x20..0x34 - Link descriptor configure and control register of Rx channel 0

pub fn in_link_ch_iter(&self) -> impl Iterator<Item = &Reg<IN_LINK_CH_SPEC>>

Iterator for array of: 0x20..0x34 - Link descriptor configure and control register of Rx channel 0

pub fn in_state_ch(&self, n: usize) -> &Reg<IN_STATE_CH_SPEC>

0x24..0x38 - Receive status of Rx channel 0

pub fn in_state_ch_iter(&self) -> impl Iterator<Item = &Reg<IN_STATE_CH_SPEC>>

Iterator for array of: 0x24..0x38 - Receive status of Rx channel 0

pub fn in_suc_eof_des_addr_ch( &self, n: usize ) -> &Reg<IN_SUC_EOF_DES_ADDR_CH_SPEC>

0x28..0x3c - Inlink descriptor address when EOF occurs of Rx channel 0

pub fn in_suc_eof_des_addr_ch_iter( &self ) -> impl Iterator<Item = &Reg<IN_SUC_EOF_DES_ADDR_CH_SPEC>>

Iterator for array of: 0x28..0x3c - Inlink descriptor address when EOF occurs of Rx channel 0

pub fn in_err_eof_des_addr_ch( &self, n: usize ) -> &Reg<IN_ERR_EOF_DES_ADDR_CH_SPEC>

0x2c..0x40 - Inlink descriptor address when errors occur of Rx channel 0

pub fn in_err_eof_des_addr_ch_iter( &self ) -> impl Iterator<Item = &Reg<IN_ERR_EOF_DES_ADDR_CH_SPEC>>

Iterator for array of: 0x2c..0x40 - Inlink descriptor address when errors occur of Rx channel 0

pub fn in_dscr_ch(&self, n: usize) -> &Reg<IN_DSCR_CH_SPEC>

0x30..0x44 - Current inlink descriptor address of Rx channel 0

pub fn in_dscr_ch_iter(&self) -> impl Iterator<Item = &Reg<IN_DSCR_CH_SPEC>>

Iterator for array of: 0x30..0x44 - Current inlink descriptor address of Rx channel 0

pub fn in_dscr_bf0_ch(&self, n: usize) -> &Reg<IN_DSCR_BF0_CH_SPEC>

0x34..0x48 - The last inlink descriptor address of Rx channel 0

pub fn in_dscr_bf0_ch_iter( &self ) -> impl Iterator<Item = &Reg<IN_DSCR_BF0_CH_SPEC>>

Iterator for array of: 0x34..0x48 - The last inlink descriptor address of Rx channel 0

pub fn in_dscr_bf1_ch(&self, n: usize) -> &Reg<IN_DSCR_BF1_CH_SPEC>

0x38..0x4c - The second-to-last inlink descriptor address of Rx channel 0

pub fn in_dscr_bf1_ch_iter( &self ) -> impl Iterator<Item = &Reg<IN_DSCR_BF1_CH_SPEC>>

Iterator for array of: 0x38..0x4c - The second-to-last inlink descriptor address of Rx channel 0

pub fn in_wight_ch(&self, n: usize) -> &Reg<IN_WIGHT_CH_SPEC>

0x3c..0x50 - Weight register of Rx channel 0

pub fn in_wight_ch_iter(&self) -> impl Iterator<Item = &Reg<IN_WIGHT_CH_SPEC>>

Iterator for array of: 0x3c..0x50 - Weight register of Rx channel 0

pub fn in_pri_ch(&self, n: usize) -> &Reg<IN_PRI_CH_SPEC>

0x44..0x58 - Priority register of Rx channel 0

pub fn in_pri_ch_iter(&self) -> impl Iterator<Item = &Reg<IN_PRI_CH_SPEC>>

Iterator for array of: 0x44..0x58 - Priority register of Rx channel 0

pub fn in_peri_sel_ch(&self, n: usize) -> &Reg<IN_PERI_SEL_CH_SPEC>

0x48..0x5c - Peripheral selection of Rx channel 0

pub fn in_peri_sel_ch_iter( &self ) -> impl Iterator<Item = &Reg<IN_PERI_SEL_CH_SPEC>>

Iterator for array of: 0x48..0x5c - Peripheral selection of Rx channel 0

pub fn out_conf0_ch(&self, n: usize) -> &Reg<OUT_CONF0_CH_SPEC>

0x60..0x74 - Configure 0 register of Tx channel 0

pub fn out_conf0_ch_iter(&self) -> impl Iterator<Item = &Reg<OUT_CONF0_CH_SPEC>>

Iterator for array of: 0x60..0x74 - Configure 0 register of Tx channel 0

pub fn out_conf1_ch(&self, n: usize) -> &Reg<OUT_CONF1_CH_SPEC>

0x64..0x78 - Configure 1 register of Tx channel 0

pub fn out_conf1_ch_iter(&self) -> impl Iterator<Item = &Reg<OUT_CONF1_CH_SPEC>>

Iterator for array of: 0x64..0x78 - Configure 1 register of Tx channel 0

pub fn out_int_raw_ch(&self, n: usize) -> &Reg<OUT_INT_RAW_CH_SPEC>

0x68..0x7c - Raw status interrupt of Tx channel 0

pub fn out_int_raw_ch_iter( &self ) -> impl Iterator<Item = &Reg<OUT_INT_RAW_CH_SPEC>>

Iterator for array of: 0x68..0x7c - Raw status interrupt of Tx channel 0

pub fn out_int_st_ch(&self, n: usize) -> &Reg<OUT_INT_ST_CH_SPEC>

0x6c..0x80 - Masked interrupt of Tx channel 0

pub fn out_int_st_ch_iter( &self ) -> impl Iterator<Item = &Reg<OUT_INT_ST_CH_SPEC>>

Iterator for array of: 0x6c..0x80 - Masked interrupt of Tx channel 0

pub fn out_int_ena_ch(&self, n: usize) -> &Reg<OUT_INT_ENA_CH_SPEC>

0x70..0x84 - Interrupt enable bits of Tx channel 0

pub fn out_int_ena_ch_iter( &self ) -> impl Iterator<Item = &Reg<OUT_INT_ENA_CH_SPEC>>

Iterator for array of: 0x70..0x84 - Interrupt enable bits of Tx channel 0

pub fn out_int_clr_ch(&self, n: usize) -> &Reg<OUT_INT_CLR_CH_SPEC>

0x74..0x88 - Interrupt clear bits of Tx channel 0

pub fn out_int_clr_ch_iter( &self ) -> impl Iterator<Item = &Reg<OUT_INT_CLR_CH_SPEC>>

Iterator for array of: 0x74..0x88 - Interrupt clear bits of Tx channel 0

pub fn outfifo_status_ch(&self, n: usize) -> &Reg<OUTFIFO_STATUS_CH_SPEC>

0x78..0x8c - Transmit FIFO status of Tx channel 0

pub fn outfifo_status_ch_iter( &self ) -> impl Iterator<Item = &Reg<OUTFIFO_STATUS_CH_SPEC>>

Iterator for array of: 0x78..0x8c - Transmit FIFO status of Tx channel 0

pub fn out_push_ch(&self, n: usize) -> &Reg<OUT_PUSH_CH_SPEC>

0x7c..0x90 - Push control register of Rx channel 0

pub fn out_push_ch_iter(&self) -> impl Iterator<Item = &Reg<OUT_PUSH_CH_SPEC>>

Iterator for array of: 0x7c..0x90 - Push control register of Rx channel 0

pub fn out_link_ch(&self, n: usize) -> &Reg<OUT_LINK_CH_SPEC>

0x80..0x94 - Link descriptor configure and control register of Tx channel 0

pub fn out_link_ch_iter(&self) -> impl Iterator<Item = &Reg<OUT_LINK_CH_SPEC>>

Iterator for array of: 0x80..0x94 - Link descriptor configure and control register of Tx channel 0

pub fn out_state_ch(&self, n: usize) -> &Reg<OUT_STATE_CH_SPEC>

0x84..0x98 - Transmit status of Tx channel 0

pub fn out_state_ch_iter(&self) -> impl Iterator<Item = &Reg<OUT_STATE_CH_SPEC>>

Iterator for array of: 0x84..0x98 - Transmit status of Tx channel 0

pub fn out_eof_des_addr_ch(&self, n: usize) -> &Reg<OUT_EOF_DES_ADDR_CH_SPEC>

0x88..0x9c - Outlink descriptor address when EOF occurs of Tx channel 0

pub fn out_eof_des_addr_ch_iter( &self ) -> impl Iterator<Item = &Reg<OUT_EOF_DES_ADDR_CH_SPEC>>

Iterator for array of: 0x88..0x9c - Outlink descriptor address when EOF occurs of Tx channel 0

pub fn out_eof_bfr_des_addr_ch( &self, n: usize ) -> &Reg<OUT_EOF_BFR_DES_ADDR_CH_SPEC>

0x8c..0xa0 - The last outlink descriptor address when EOF occurs of Tx channel 0

pub fn out_eof_bfr_des_addr_ch_iter( &self ) -> impl Iterator<Item = &Reg<OUT_EOF_BFR_DES_ADDR_CH_SPEC>>

Iterator for array of: 0x8c..0xa0 - The last outlink descriptor address when EOF occurs of Tx channel 0

pub fn out_dscr_ch(&self, n: usize) -> &Reg<OUT_DSCR_CH_SPEC>

0x90..0xa4 - Current inlink descriptor address of Tx channel 0

pub fn out_dscr_ch_iter(&self) -> impl Iterator<Item = &Reg<OUT_DSCR_CH_SPEC>>

Iterator for array of: 0x90..0xa4 - Current inlink descriptor address of Tx channel 0

pub fn out_dscr_bf0_ch(&self, n: usize) -> &Reg<OUT_DSCR_BF0_CH_SPEC>

0x94..0xa8 - The last inlink descriptor address of Tx channel 0

pub fn out_dscr_bf0_ch_iter( &self ) -> impl Iterator<Item = &Reg<OUT_DSCR_BF0_CH_SPEC>>

Iterator for array of: 0x94..0xa8 - The last inlink descriptor address of Tx channel 0

pub fn out_dscr_bf1_ch(&self, n: usize) -> &Reg<OUT_DSCR_BF1_CH_SPEC>

0x98..0xac - The second-to-last inlink descriptor address of Tx channel 0

pub fn out_dscr_bf1_ch_iter( &self ) -> impl Iterator<Item = &Reg<OUT_DSCR_BF1_CH_SPEC>>

Iterator for array of: 0x98..0xac - The second-to-last inlink descriptor address of Tx channel 0

pub fn out_wight_ch(&self, n: usize) -> &Reg<OUT_WIGHT_CH_SPEC>

0x9c..0xb0 - Weight register of Rx channel 0

pub fn out_wight_ch_iter(&self) -> impl Iterator<Item = &Reg<OUT_WIGHT_CH_SPEC>>

Iterator for array of: 0x9c..0xb0 - Weight register of Rx channel 0

pub fn out_pri_ch(&self, n: usize) -> &Reg<OUT_PRI_CH_SPEC>

0xa4..0xb8 - Priority register of Tx channel 0.

pub fn out_pri_ch_iter(&self) -> impl Iterator<Item = &Reg<OUT_PRI_CH_SPEC>>

Iterator for array of: 0xa4..0xb8 - Priority register of Tx channel 0.

pub fn out_peri_sel_ch(&self, n: usize) -> &Reg<OUT_PERI_SEL_CH_SPEC>

0xa8..0xbc - Peripheral selection of Tx channel 0

pub fn out_peri_sel_ch_iter( &self ) -> impl Iterator<Item = &Reg<OUT_PERI_SEL_CH_SPEC>>

Iterator for array of: 0xa8..0xbc - Peripheral selection of Tx channel 0

pub fn ahb_test(&self) -> &Reg<AHB_TEST_SPEC>

0x3c0 - reserved

pub fn pd_conf(&self) -> &Reg<PD_CONF_SPEC>

0x3c4 - reserved

pub fn misc_conf(&self) -> &Reg<MISC_CONF_SPEC>

0x3c8 - MISC register

pub fn in_sram_size_ch(&self, n: usize) -> &Reg<IN_SRAM_SIZE_CH_SPEC>

0x3cc..0x3e0 - Receive L2 FIFO depth of Rx channel 0

pub fn in_sram_size_ch_iter( &self ) -> impl Iterator<Item = &Reg<IN_SRAM_SIZE_CH_SPEC>>

Iterator for array of: 0x3cc..0x3e0 - Receive L2 FIFO depth of Rx channel 0

pub fn out_sram_size_ch(&self, n: usize) -> &Reg<OUT_SRAM_SIZE_CH_SPEC>

0x3d0..0x3e4 - Transmit L2 FIFO depth of Tx channel 0

pub fn out_sram_size_ch_iter( &self ) -> impl Iterator<Item = &Reg<OUT_SRAM_SIZE_CH_SPEC>>

Iterator for array of: 0x3d0..0x3e4 - Transmit L2 FIFO depth of Tx channel 0

pub fn extmem_reject_addr(&self) -> &Reg<EXTMEM_REJECT_ADDR_SPEC>

0x3f4 - Reject address accessing external RAM

pub fn extmem_reject_st(&self) -> &Reg<EXTMEM_REJECT_ST_SPEC>

0x3f8 - Reject status accessing external RAM

pub fn extmem_reject_int_raw(&self) -> &Reg<EXTMEM_REJECT_INT_RAW_SPEC>

0x3fc - Raw interrupt status of external RAM permission

pub fn extmem_reject_int_st(&self) -> &Reg<EXTMEM_REJECT_INT_ST_SPEC>

0x400 - Masked interrupt status of external RAM permission

pub fn extmem_reject_int_ena(&self) -> &Reg<EXTMEM_REJECT_INT_ENA_SPEC>

0x404 - Interrupt enable bits of external RAM permission

pub fn extmem_reject_int_clr(&self) -> &Reg<EXTMEM_REJECT_INT_CLR_SPEC>

0x408 - Interrupt clear bits of external RAM permission

pub fn date(&self) -> &Reg<DATE_SPEC>

0x40c - Version control register

Trait Implementations

impl Debug for DMA

fn fmt(&self, f: &mut Formatter<'_>) -> Result<(), Error>

Formats the value using the given formatter.

impl Deref for DMA

type Target = <DMA as Deref>::Target

The resulting type after dereferencing.

fn deref(&self) -> &<DMA as Deref>::Target

Dereferences the value.

impl DerefMut for DMA

fn deref_mut(&mut self) -> &mut <DMA as Deref>::Target

Mutably dereferences the value.

impl Peripheral for DMA

type P = DMA

Peripheral singleton type

unsafe fn clone_unchecked(&mut self) -> <DMA as Peripheral>::P

Unsafely clone (duplicate) a peripheral singleton.

fn into_ref<'a>(self) -> PeripheralRef<'a, Self::P>

where Self: 'a,

Convert a value into a PeripheralRef.