Struct esp32s3_hal::peripherals::SPI2

pub struct SPI2 { /* private fields */ }

Implementations

impl SPI2

pub unsafe fn steal() -> SPI2

Unsafely create an instance of this peripheral out of thin air.

Safety

You must ensure that you’re only using one instance of this type at a time.

pub const PTR: *const <SPI2 as Deref>::Target = {0x60024000 as *const <esp32s3::SPI2 as core::ops::Deref>::Target}

Pointer to the register block

pub const fn ptr() -> *const <SPI2 as Deref>::Target

Return the pointer to the register block

Methods from Deref<Target = RegisterBlock>

pub fn cmd(&self) -> &Reg<CMD_SPEC>

0x00 - Command control register

pub fn addr(&self) -> &Reg<ADDR_SPEC>

0x04 - Address value register

pub fn ctrl(&self) -> &Reg<CTRL_SPEC>

0x08 - SPI control register

pub fn clock(&self) -> &Reg<CLOCK_SPEC>

0x0c - SPI clock control register

pub fn user(&self) -> &Reg<USER_SPEC>

0x10 - SPI USER control register

pub fn user1(&self) -> &Reg<USER1_SPEC>

0x14 - SPI USER control register 1

pub fn user2(&self) -> &Reg<USER2_SPEC>

0x18 - SPI USER control register 2

pub fn ms_dlen(&self) -> &Reg<MS_DLEN_SPEC>

0x1c - SPI data bit length control register

pub fn misc(&self) -> &Reg<MISC_SPEC>

0x20 - SPI misc register

pub fn din_mode(&self) -> &Reg<DIN_MODE_SPEC>

0x24 - SPI input delay mode configuration

pub fn din_num(&self) -> &Reg<DIN_NUM_SPEC>

0x28 - SPI input delay number configuration

pub fn dout_mode(&self) -> &Reg<DOUT_MODE_SPEC>

0x2c - SPI output delay mode configuration

pub fn dma_conf(&self) -> &Reg<DMA_CONF_SPEC>

0x30 - SPI DMA control register

pub fn dma_int_ena(&self) -> &Reg<DMA_INT_ENA_SPEC>

0x34 - SPI interrupt enable register

pub fn dma_int_clr(&self) -> &Reg<DMA_INT_CLR_SPEC>

0x38 - SPI interrupt clear register

pub fn dma_int_raw(&self) -> &Reg<DMA_INT_RAW_SPEC>

0x3c - SPI interrupt raw register

pub fn dma_int_st(&self) -> &Reg<DMA_INT_ST_SPEC>

0x40 - SPI interrupt status register

pub fn dma_int_set(&self) -> &Reg<DMA_INT_SET_SPEC>

0x44 - SPI interrupt software set register

pub fn w0(&self) -> &Reg<W0_SPEC>

0x98 - SPI CPU-controlled buffer0

pub fn w1(&self) -> &Reg<W1_SPEC>

0x9c - SPI CPU-controlled buffer1

pub fn w2(&self) -> &Reg<W2_SPEC>

0xa0 - SPI CPU-controlled buffer2

pub fn w3(&self) -> &Reg<W3_SPEC>

0xa4 - SPI CPU-controlled buffer3

pub fn w4(&self) -> &Reg<W4_SPEC>

0xa8 - SPI CPU-controlled buffer4

pub fn w5(&self) -> &Reg<W5_SPEC>

0xac - SPI CPU-controlled buffer5

pub fn w6(&self) -> &Reg<W6_SPEC>

0xb0 - SPI CPU-controlled buffer6

pub fn w7(&self) -> &Reg<W7_SPEC>

0xb4 - SPI CPU-controlled buffer7

pub fn w8(&self) -> &Reg<W8_SPEC>

0xb8 - SPI CPU-controlled buffer8

pub fn w9(&self) -> &Reg<W9_SPEC>

0xbc - SPI CPU-controlled buffer9

pub fn w10(&self) -> &Reg<W10_SPEC>

0xc0 - SPI CPU-controlled buffer10

pub fn w11(&self) -> &Reg<W11_SPEC>

0xc4 - SPI CPU-controlled buffer11

pub fn w12(&self) -> &Reg<W12_SPEC>

0xc8 - SPI CPU-controlled buffer12

pub fn w13(&self) -> &Reg<W13_SPEC>

0xcc - SPI CPU-controlled buffer13

pub fn w14(&self) -> &Reg<W14_SPEC>

0xd0 - SPI CPU-controlled buffer14

pub fn w15(&self) -> &Reg<W15_SPEC>

0xd4 - SPI CPU-controlled buffer15

pub fn slave(&self) -> &Reg<SLAVE_SPEC>

0xe0 - SPI slave control register

pub fn slave1(&self) -> &Reg<SLAVE1_SPEC>

0xe4 - SPI slave control register 1

pub fn clk_gate(&self) -> &Reg<CLK_GATE_SPEC>

0xe8 - SPI module clock and register clock control

pub fn date(&self) -> &Reg<DATE_SPEC>

0xf0 - Version control

Trait Implementations

impl Debug for SPI2

fn fmt(&self, f: &mut Formatter<'_>) -> Result<(), Error>

Formats the value using the given formatter.

impl Deref for SPI2

type Target = <SPI2 as Deref>::Target

The resulting type after dereferencing.

fn deref(&self) -> &<SPI2 as Deref>::Target

Dereferences the value.

impl DerefMut for SPI2

fn deref_mut(&mut self) -> &mut <SPI2 as Deref>::Target

Mutably dereferences the value.

impl ExtendedInstance for SPI2

fn sio0_input_signal(&self) -> InputSignal

fn sio1_output_signal(&self) -> OutputSignal

fn sio2_output_signal(&self) -> OutputSignal

fn sio2_input_signal(&self) -> InputSignal

fn sio3_output_signal(&self) -> OutputSignal

fn sio3_input_signal(&self) -> InputSignal

impl Instance for SPI2

fn register_block(&self) -> &RegisterBlock

fn sclk_signal(&self) -> InputSignal

fn mosi_signal(&self) -> InputSignal

fn miso_signal(&self) -> OutputSignal

fn cs_signal(&self) -> InputSignal

fn enable_peripheral(&self)

fn spi_num(&self) -> u8

fn init(&mut self)

Initialize for full-duplex 1 bit mode

fn set_data_mode(&mut self, data_mode: SpiMode) -> &mut Self

fn is_bus_busy(&self) -> bool

fn flush(&mut self) -> Result<(), Error>

fn setup_for_flush(&self)

impl Instance for SPI2

fn register_block(&self) -> &RegisterBlock

fn sclk_signal(&self) -> OutputSignal

fn mosi_signal(&self) -> OutputSignal

fn miso_signal(&self) -> InputSignal

fn cs_signal(&self) -> OutputSignal

fn enable_peripheral(&self)

fn spi_num(&self) -> u8

fn init(&mut self)

Initialize for full-duplex 1 bit mode

fn init_spi_data_mode( &mut self, cmd_mode: SpiDataMode, address_mode: SpiDataMode, data_mode: SpiDataMode )

fn setup(&mut self, frequency: Rate<u32, 1, 1>, clocks: &Clocks<'_>)

fn set_data_mode(&mut self, data_mode: SpiMode) -> &mut Self

fn ch_bus_freq(&mut self, frequency: Rate<u32, 1, 1>, clocks: &Clocks<'_>)

fn read_byte(&mut self) -> Result<u8, Error<Error>>

fn write_byte(&mut self, word: u8) -> Result<(), Error<Error>>

fn write_bytes(&mut self, words: &[u8]) -> Result<(), Error>

Write bytes to SPI.

fn read_bytes(&mut self, words: &mut [u8]) -> Result<(), Error>

Read bytes from SPI.

fn read_bytes_from_fifo(&mut self, words: &mut [u8]) -> Result<(), Error>

Read received bytes from SPI FIFO.

fn busy(&self) -> bool

fn flush(&mut self) -> Result<(), Error>

fn transfer<'w>(&mut self, words: &'w mut [u8]) -> Result<&'w [u8], Error>

fn start_operation(&self)

fn init_half_duplex( &mut self, is_write: bool, command_state: bool, address_state: bool, dummy_idle: bool, dummy_state: bool, no_mosi_miso: bool )

fn write_bytes_half_duplex( &mut self, cmd: Command, address: Address, dummy: u8, buffer: &[u8] ) -> Result<(), Error>

fn read_bytes_half_duplex( &mut self, cmd: Command, address: Address, dummy: u8, buffer: &mut [u8] ) -> Result<(), Error>

fn update(&self)

fn configure_datalen(&self, len: u32)

impl<TX, RX> InstanceDma<TX, RX> for SPI2

where TX: Tx, RX: Rx,

fn transfer_in_place_dma<'w>( &mut self, words: &'w mut [u8], tx: &mut TX, rx: &mut RX ) -> Result<&'w [u8], Error>

fn transfer_dma<'w>( &mut self, write_buffer: &'w [u8], read_buffer: &'w mut [u8], tx: &mut TX, rx: &mut RX ) -> Result<&'w [u8], Error>

fn start_transfer_dma<'w>( &mut self, write_buffer_ptr: *const u8, write_buffer_len: usize, read_buffer_ptr: *mut u8, read_buffer_len: usize, tx: &mut TX, rx: &mut RX, listen: bool ) -> Result<(), Error>

fn write_bytes_dma<'w>( &mut self, words: &'w [u8], tx: &mut TX ) -> Result<&'w [u8], Error>

fn start_write_bytes_dma<'w>( &mut self, ptr: *const u8, len: usize, tx: &mut TX, listen: bool ) -> Result<(), Error>

fn start_read_bytes_dma<'w>( &mut self, ptr: *mut u8, len: usize, rx: &mut RX, listen: bool ) -> Result<(), Error>

fn dma_peripheral(&self) -> DmaPeripheral

fn enable_dma(&self)

fn clear_dma_interrupts(&self)

impl<TX, RX> InstanceDma<TX, RX> for SPI2

where TX: Tx, RX: Rx,

fn start_transfer_dma( &mut self, write_buffer_ptr: *const u8, write_buffer_len: usize, read_buffer_ptr: *mut u8, read_buffer_len: usize, tx: &mut TX, rx: &mut RX ) -> Result<(), Error>

fn start_write_bytes_dma( &mut self, ptr: *const u8, len: usize, tx: &mut TX ) -> Result<(), Error>

fn start_read_bytes_dma( &mut self, ptr: *mut u8, len: usize, rx: &mut RX ) -> Result<(), Error>

fn dma_peripheral(&self) -> DmaPeripheral

fn enable_dma(&self)

fn clear_dma_interrupts(&self)

impl Peripheral for SPI2

type P = SPI2

Peripheral singleton type

unsafe fn clone_unchecked(&mut self) -> <SPI2 as Peripheral>::P

Unsafely clone (duplicate) a peripheral singleton.

fn into_ref<'a>(self) -> PeripheralRef<'a, Self::P>

where Self: 'a,

Convert a value into a PeripheralRef.