Struct esp32s3_hal::peripherals::WCL

pub struct WCL { /* private fields */ }

Implementations

impl WCL

pub unsafe fn steal() -> WCL

Unsafely create an instance of this peripheral out of thin air.

Safety

You must ensure that you’re only using one instance of this type at a time.

pub const PTR: *const <WCL as Deref>::Target = {0x600d0000 as *const <esp32s3::WCL as core::ops::Deref>::Target}

Pointer to the register block

pub const fn ptr() -> *const <WCL as Deref>::Target

Return the pointer to the register block

Methods from Deref<Target = RegisterBlock>

pub fn core_0_entry_1_addr(&self) -> &Reg<CORE_0_ENTRY_1_ADDR_SPEC>

0x00 - Core_0 Entry 1 address configuration Register

pub fn core_0_entry_2_addr(&self) -> &Reg<CORE_0_ENTRY_2_ADDR_SPEC>

0x04 - Core_0 Entry 2 address configuration Register

pub fn core_0_entry_3_addr(&self) -> &Reg<CORE_0_ENTRY_3_ADDR_SPEC>

0x08 - Core_0 Entry 3 address configuration Register

pub fn core_0_entry_4_addr(&self) -> &Reg<CORE_0_ENTRY_4_ADDR_SPEC>

0x0c - Core_0 Entry 4 address configuration Register

pub fn core_0_entry_5_addr(&self) -> &Reg<CORE_0_ENTRY_5_ADDR_SPEC>

0x10 - Core_0 Entry 5 address configuration Register

pub fn core_0_entry_6_addr(&self) -> &Reg<CORE_0_ENTRY_6_ADDR_SPEC>

0x14 - Core_0 Entry 6 address configuration Register

pub fn core_0_entry_7_addr(&self) -> &Reg<CORE_0_ENTRY_7_ADDR_SPEC>

0x18 - Core_0 Entry 7 address configuration Register

pub fn core_0_entry_8_addr(&self) -> &Reg<CORE_0_ENTRY_8_ADDR_SPEC>

0x1c - Core_0 Entry 8 address configuration Register

pub fn core_0_entry_9_addr(&self) -> &Reg<CORE_0_ENTRY_9_ADDR_SPEC>

0x20 - Core_0 Entry 9 address configuration Register

pub fn core_0_entry_10_addr(&self) -> &Reg<CORE_0_ENTRY_10_ADDR_SPEC>

0x24 - Core_0 Entry 10 address configuration Register

pub fn core_0_entry_11_addr(&self) -> &Reg<CORE_0_ENTRY_11_ADDR_SPEC>

0x28 - Core_0 Entry 11 address configuration Register

pub fn core_0_entry_12_addr(&self) -> &Reg<CORE_0_ENTRY_12_ADDR_SPEC>

0x2c - Core_0 Entry 12 address configuration Register

pub fn core_0_entry_13_addr(&self) -> &Reg<CORE_0_ENTRY_13_ADDR_SPEC>

0x30 - Core_0 Entry 13 address configuration Register

pub fn core_0_entry_check(&self) -> &Reg<CORE_0_ENTRY_CHECK_SPEC>

0x7c - Core_0 Entry check configuration Register

pub fn core_0_statustable1(&self) -> &Reg<CORE_0_STATUSTABLE1_SPEC>

0x80 - Status register of world switch of entry 1

pub fn core_0_statustable2(&self) -> &Reg<CORE_0_STATUSTABLE2_SPEC>

0x84 - Status register of world switch of entry 2

pub fn core_0_statustable3(&self) -> &Reg<CORE_0_STATUSTABLE3_SPEC>

0x88 - Status register of world switch of entry 3

pub fn core_0_statustable4(&self) -> &Reg<CORE_0_STATUSTABLE4_SPEC>

0x8c - Status register of world switch of entry 4

pub fn core_0_statustable5(&self) -> &Reg<CORE_0_STATUSTABLE5_SPEC>

0x90 - Status register of world switch of entry 5

pub fn core_0_statustable6(&self) -> &Reg<CORE_0_STATUSTABLE6_SPEC>

0x94 - Status register of world switch of entry 6

pub fn core_0_statustable7(&self) -> &Reg<CORE_0_STATUSTABLE7_SPEC>

0x98 - Status register of world switch of entry 7

pub fn core_0_statustable8(&self) -> &Reg<CORE_0_STATUSTABLE8_SPEC>

0x9c - Status register of world switch of entry 8

pub fn core_0_statustable9(&self) -> &Reg<CORE_0_STATUSTABLE9_SPEC>

0xa0 - Status register of world switch of entry 9

pub fn core_0_statustable10(&self) -> &Reg<CORE_0_STATUSTABLE10_SPEC>

0xa4 - Status register of world switch of entry 10

pub fn core_0_statustable11(&self) -> &Reg<CORE_0_STATUSTABLE11_SPEC>

0xa8 - Status register of world switch of entry 11

pub fn core_0_statustable12(&self) -> &Reg<CORE_0_STATUSTABLE12_SPEC>

0xac - Status register of world switch of entry 12

pub fn core_0_statustable13(&self) -> &Reg<CORE_0_STATUSTABLE13_SPEC>

0xb0 - Status register of world switch of entry 13

pub fn core_0_statustable_current( &self ) -> &Reg<CORE_0_STATUSTABLE_CURRENT_SPEC>

0xfc - Status register of statustable current

pub fn core_0_message_addr(&self) -> &Reg<CORE_0_MESSAGE_ADDR_SPEC>

0x100 - Clear writer_buffer write address configuration register

pub fn core_0_message_max(&self) -> &Reg<CORE_0_MESSAGE_MAX_SPEC>

0x104 - Clear writer_buffer write number configuration register

pub fn core_0_message_phase(&self) -> &Reg<CORE_0_MESSAGE_PHASE_SPEC>

0x108 - Clear writer_buffer status register

pub fn core_0_world_trigger_addr(&self) -> &Reg<CORE_0_WORLD_TRIGGER_ADDR_SPEC>

0x140 - Core_0 trigger address configuration Register

pub fn core_0_world_prepare(&self) -> &Reg<CORE_0_WORLD_PREPARE_SPEC>

0x144 - Core_0 prepare world configuration Register

pub fn core_0_world_update(&self) -> &Reg<CORE_0_WORLD_UPDATE_SPEC>

0x148 - Core_0 configuration update register

pub fn core_0_world_cancel(&self) -> &Reg<CORE_0_WORLD_CANCEL_SPEC>

0x14c - Core_0 configuration cancel register

pub fn core_0_world_iram0(&self) -> &Reg<CORE_0_WORLD_IRAM0_SPEC>

0x150 - Core_0 Iram0 world register

pub fn core_0_world_dram0_pif(&self) -> &Reg<CORE_0_WORLD_DRAM0_PIF_SPEC>

0x154 - Core_0 dram0 and PIF world register

pub fn core_0_world_phase(&self) -> &Reg<CORE_0_WORLD_PHASE_SPEC>

0x158 - Core_0 world status register

pub fn core_0_nmi_mask_enable(&self) -> &Reg<CORE_0_NMI_MASK_ENABLE_SPEC>

0x180 - Core_0 NMI mask enable register

pub fn core_0_nmi_mask_trigger_addr( &self ) -> &Reg<CORE_0_NMI_MASK_TRIGGER_ADDR_SPEC>

0x184 - Core_0 NMI mask trigger address register

pub fn core_0_nmi_mask_disable(&self) -> &Reg<CORE_0_NMI_MASK_DISABLE_SPEC>

0x188 - Core_0 NMI mask disable register

pub fn core_0_nmi_mask_cancle(&self) -> &Reg<CORE_0_NMI_MASK_CANCLE_SPEC>

0x18c - Core_0 NMI mask disable register

pub fn core_0_nmi_mask(&self) -> &Reg<CORE_0_NMI_MASK_SPEC>

0x190 - Core_0 NMI mask register

pub fn core_0_nmi_mask_phase(&self) -> &Reg<CORE_0_NMI_MASK_PHASE_SPEC>

0x194 - Core_0 NMI mask phase register

pub fn core_1_entry_1_addr(&self) -> &Reg<CORE_1_ENTRY_1_ADDR_SPEC>

0x400 - Core_1 Entry 1 address configuration Register

pub fn core_1_entry_2_addr(&self) -> &Reg<CORE_1_ENTRY_2_ADDR_SPEC>

0x404 - Core_1 Entry 2 address configuration Register

pub fn core_1_entry_3_addr(&self) -> &Reg<CORE_1_ENTRY_3_ADDR_SPEC>

0x408 - Core_1 Entry 3 address configuration Register

pub fn core_1_entry_4_addr(&self) -> &Reg<CORE_1_ENTRY_4_ADDR_SPEC>

0x40c - Core_1 Entry 4 address configuration Register

pub fn core_1_entry_5_addr(&self) -> &Reg<CORE_1_ENTRY_5_ADDR_SPEC>

0x410 - Core_1 Entry 5 address configuration Register

pub fn core_1_entry_6_addr(&self) -> &Reg<CORE_1_ENTRY_6_ADDR_SPEC>

0x414 - Core_1 Entry 6 address configuration Register

pub fn core_1_entry_7_addr(&self) -> &Reg<CORE_1_ENTRY_7_ADDR_SPEC>

0x418 - Core_1 Entry 7 address configuration Register

pub fn core_1_entry_8_addr(&self) -> &Reg<CORE_1_ENTRY_8_ADDR_SPEC>

0x41c - Core_1 Entry 8 address configuration Register

pub fn core_1_entry_9_addr(&self) -> &Reg<CORE_1_ENTRY_9_ADDR_SPEC>

0x420 - Core_1 Entry 9 address configuration Register

pub fn core_1_entry_10_addr(&self) -> &Reg<CORE_1_ENTRY_10_ADDR_SPEC>

0x424 - Core_1 Entry 10 address configuration Register

pub fn core_1_entry_11_addr(&self) -> &Reg<CORE_1_ENTRY_11_ADDR_SPEC>

0x428 - Core_1 Entry 11 address configuration Register

pub fn core_1_entry_12_addr(&self) -> &Reg<CORE_1_ENTRY_12_ADDR_SPEC>

0x42c - Core_1 Entry 12 address configuration Register

pub fn core_1_entry_13_addr(&self) -> &Reg<CORE_1_ENTRY_13_ADDR_SPEC>

0x430 - Core_1 Entry 13 address configuration Register

pub fn core_1_entry_check(&self) -> &Reg<CORE_1_ENTRY_CHECK_SPEC>

0x47c - Core_1 Entry check configuration Register

pub fn core_1_statustable1(&self) -> &Reg<CORE_1_STATUSTABLE1_SPEC>

0x480 - Status register of world switch of entry 1

pub fn core_1_statustable2(&self) -> &Reg<CORE_1_STATUSTABLE2_SPEC>

0x484 - Status register of world switch of entry 2

pub fn core_1_statustable3(&self) -> &Reg<CORE_1_STATUSTABLE3_SPEC>

0x488 - Status register of world switch of entry 3

pub fn core_1_statustable4(&self) -> &Reg<CORE_1_STATUSTABLE4_SPEC>

0x48c - Status register of world switch of entry 4

pub fn core_1_statustable5(&self) -> &Reg<CORE_1_STATUSTABLE5_SPEC>

0x490 - Status register of world switch of entry 5

pub fn core_1_statustable6(&self) -> &Reg<CORE_1_STATUSTABLE6_SPEC>

0x494 - Status register of world switch of entry 6

pub fn core_1_statustable7(&self) -> &Reg<CORE_1_STATUSTABLE7_SPEC>

0x498 - Status register of world switch of entry 7

pub fn core_1_statustable8(&self) -> &Reg<CORE_1_STATUSTABLE8_SPEC>

0x49c - Status register of world switch of entry 8

pub fn core_1_statustable9(&self) -> &Reg<CORE_1_STATUSTABLE9_SPEC>

0x4a0 - Status register of world switch of entry 9

pub fn core_1_statustable10(&self) -> &Reg<CORE_1_STATUSTABLE10_SPEC>

0x4a4 - Status register of world switch of entry 10

pub fn core_1_statustable11(&self) -> &Reg<CORE_1_STATUSTABLE11_SPEC>

0x4a8 - Status register of world switch of entry 11

pub fn core_1_statustable12(&self) -> &Reg<CORE_1_STATUSTABLE12_SPEC>

0x4ac - Status register of world switch of entry 12

pub fn core_1_statustable13(&self) -> &Reg<CORE_1_STATUSTABLE13_SPEC>

0x4b0 - Status register of world switch of entry 13

pub fn core_1_statustable_current( &self ) -> &Reg<CORE_1_STATUSTABLE_CURRENT_SPEC>

0x4fc - Status register of statustable current

pub fn core_1_message_addr(&self) -> &Reg<CORE_1_MESSAGE_ADDR_SPEC>

0x500 - Clear writer_buffer write address configuration register

pub fn core_1_message_max(&self) -> &Reg<CORE_1_MESSAGE_MAX_SPEC>

0x504 - Clear writer_buffer write number configuration register

pub fn core_1_message_phase(&self) -> &Reg<CORE_1_MESSAGE_PHASE_SPEC>

0x508 - Clear writer_buffer status register

pub fn core_1_world_trigger_addr(&self) -> &Reg<CORE_1_WORLD_TRIGGER_ADDR_SPEC>

0x540 - Core_1 trigger address configuration Register

pub fn core_1_world_prepare(&self) -> &Reg<CORE_1_WORLD_PREPARE_SPEC>

0x544 - Core_1 prepare world configuration Register

pub fn core_1_world_update(&self) -> &Reg<CORE_1_WORLD_UPDATE_SPEC>

0x548 - Core_1 configuration update register

pub fn core_1_world_cancel(&self) -> &Reg<CORE_1_WORLD_CANCEL_SPEC>

0x54c - Core_1 configuration cancel register

pub fn core_1_world_iram0(&self) -> &Reg<CORE_1_WORLD_IRAM0_SPEC>

0x550 - Core_1 Iram0 world register

pub fn core_1_world_dram0_pif(&self) -> &Reg<CORE_1_WORLD_DRAM0_PIF_SPEC>

0x554 - Core_1 dram0 and PIF world register

pub fn core_1_world_phase(&self) -> &Reg<CORE_1_WORLD_PHASE_SPEC>

0x558 - Core_0 world status register

pub fn core_1_nmi_mask_enable(&self) -> &Reg<CORE_1_NMI_MASK_ENABLE_SPEC>

0x580 - Core_1 NMI mask enable register

pub fn core_1_nmi_mask_trigger_addr( &self ) -> &Reg<CORE_1_NMI_MASK_TRIGGER_ADDR_SPEC>

0x584 - Core_1 NMI mask trigger addr register

pub fn core_1_nmi_mask_disable(&self) -> &Reg<CORE_1_NMI_MASK_DISABLE_SPEC>

0x588 - Core_1 NMI mask disable register

pub fn core_1_nmi_mask_cancle(&self) -> &Reg<CORE_1_NMI_MASK_CANCLE_SPEC>

0x58c - Core_1 NMI mask disable register

pub fn core_1_nmi_mask(&self) -> &Reg<CORE_1_NMI_MASK_SPEC>

0x590 - Core_1 NMI mask register

pub fn core_1_nmi_mask_phase(&self) -> &Reg<CORE_1_NMI_MASK_PHASE_SPEC>

0x594 - Core_1 NMI mask phase register

Trait Implementations

impl Debug for WCL

fn fmt(&self, f: &mut Formatter<'_>) -> Result<(), Error>

Formats the value using the given formatter.

impl Deref for WCL

type Target = <WCL as Deref>::Target

The resulting type after dereferencing.

fn deref(&self) -> &<WCL as Deref>::Target

Dereferences the value.

impl DerefMut for WCL

fn deref_mut(&mut self) -> &mut <WCL as Deref>::Target

Mutably dereferences the value.

impl Peripheral for WCL

type P = WCL

Peripheral singleton type

unsafe fn clone_unchecked(&mut self) -> <WCL as Peripheral>::P

Unsafely clone (duplicate) a peripheral singleton.

fn into_ref<'a>(self) -> PeripheralRef<'a, Self::P>

where Self: 'a,

Convert a value into a PeripheralRef.