Struct esp32s3_hal::peripherals::LEDC
source · pub struct LEDC { /* private fields */ }
Implementations§
source§impl LEDC
impl LEDC
sourcepub unsafe fn steal() -> LEDC
pub unsafe fn steal() -> LEDC
Unsafely create an instance of this peripheral out of thin air.
Safety
You must ensure that you’re only using one instance of this type at a time.
Methods from Deref<Target = RegisterBlock>§
pub fn ch_conf0(&self, n: usize) -> &Reg<CH_CONF0_SPEC>
pub fn ch_conf0(&self, n: usize) -> &Reg<CH_CONF0_SPEC>
0x00..0x20 - Configuration register 0 for channel %s
pub fn ch_conf0_iter(&self) -> impl Iterator<Item = &Reg<CH_CONF0_SPEC>>
pub fn ch_conf0_iter(&self) -> impl Iterator<Item = &Reg<CH_CONF0_SPEC>>
Iterator for array of: 0x00..0x20 - Configuration register 0 for channel %s
pub fn ch0_conf0(&self) -> &Reg<CH_CONF0_SPEC>
pub fn ch0_conf0(&self) -> &Reg<CH_CONF0_SPEC>
0x00 - Configuration register 0 for channel 0
pub fn ch1_conf0(&self) -> &Reg<CH_CONF0_SPEC>
pub fn ch1_conf0(&self) -> &Reg<CH_CONF0_SPEC>
0x14 - Configuration register 0 for channel 1
pub fn ch2_conf0(&self) -> &Reg<CH_CONF0_SPEC>
pub fn ch2_conf0(&self) -> &Reg<CH_CONF0_SPEC>
0x28 - Configuration register 0 for channel 2
pub fn ch3_conf0(&self) -> &Reg<CH_CONF0_SPEC>
pub fn ch3_conf0(&self) -> &Reg<CH_CONF0_SPEC>
0x3c - Configuration register 0 for channel 3
pub fn ch4_conf0(&self) -> &Reg<CH_CONF0_SPEC>
pub fn ch4_conf0(&self) -> &Reg<CH_CONF0_SPEC>
0x50 - Configuration register 0 for channel 4
pub fn ch5_conf0(&self) -> &Reg<CH_CONF0_SPEC>
pub fn ch5_conf0(&self) -> &Reg<CH_CONF0_SPEC>
0x64 - Configuration register 0 for channel 5
pub fn ch6_conf0(&self) -> &Reg<CH_CONF0_SPEC>
pub fn ch6_conf0(&self) -> &Reg<CH_CONF0_SPEC>
0x78 - Configuration register 0 for channel 6
pub fn ch7_conf0(&self) -> &Reg<CH_CONF0_SPEC>
pub fn ch7_conf0(&self) -> &Reg<CH_CONF0_SPEC>
0x8c - Configuration register 0 for channel 7
pub fn ch_hpoint(&self, n: usize) -> &Reg<CH_HPOINT_SPEC>
pub fn ch_hpoint(&self, n: usize) -> &Reg<CH_HPOINT_SPEC>
0x04..0x24 - High point register for channel %s
pub fn ch_hpoint_iter(&self) -> impl Iterator<Item = &Reg<CH_HPOINT_SPEC>>
pub fn ch_hpoint_iter(&self) -> impl Iterator<Item = &Reg<CH_HPOINT_SPEC>>
Iterator for array of: 0x04..0x24 - High point register for channel %s
pub fn ch0_hpoint(&self) -> &Reg<CH_HPOINT_SPEC>
pub fn ch0_hpoint(&self) -> &Reg<CH_HPOINT_SPEC>
0x04 - High point register for channel 0
pub fn ch1_hpoint(&self) -> &Reg<CH_HPOINT_SPEC>
pub fn ch1_hpoint(&self) -> &Reg<CH_HPOINT_SPEC>
0x18 - High point register for channel 1
pub fn ch2_hpoint(&self) -> &Reg<CH_HPOINT_SPEC>
pub fn ch2_hpoint(&self) -> &Reg<CH_HPOINT_SPEC>
0x2c - High point register for channel 2
pub fn ch3_hpoint(&self) -> &Reg<CH_HPOINT_SPEC>
pub fn ch3_hpoint(&self) -> &Reg<CH_HPOINT_SPEC>
0x40 - High point register for channel 3
pub fn ch4_hpoint(&self) -> &Reg<CH_HPOINT_SPEC>
pub fn ch4_hpoint(&self) -> &Reg<CH_HPOINT_SPEC>
0x54 - High point register for channel 4
pub fn ch5_hpoint(&self) -> &Reg<CH_HPOINT_SPEC>
pub fn ch5_hpoint(&self) -> &Reg<CH_HPOINT_SPEC>
0x68 - High point register for channel 5
pub fn ch6_hpoint(&self) -> &Reg<CH_HPOINT_SPEC>
pub fn ch6_hpoint(&self) -> &Reg<CH_HPOINT_SPEC>
0x7c - High point register for channel 6
pub fn ch7_hpoint(&self) -> &Reg<CH_HPOINT_SPEC>
pub fn ch7_hpoint(&self) -> &Reg<CH_HPOINT_SPEC>
0x90 - High point register for channel 7
pub fn ch_duty_iter(&self) -> impl Iterator<Item = &Reg<CH_DUTY_SPEC>>
pub fn ch_duty_iter(&self) -> impl Iterator<Item = &Reg<CH_DUTY_SPEC>>
Iterator for array of: 0x08..0x28 - Initial duty cycle for channel %s
pub fn ch0_duty(&self) -> &Reg<CH_DUTY_SPEC>
pub fn ch0_duty(&self) -> &Reg<CH_DUTY_SPEC>
0x08 - Initial duty cycle for channel 0
pub fn ch1_duty(&self) -> &Reg<CH_DUTY_SPEC>
pub fn ch1_duty(&self) -> &Reg<CH_DUTY_SPEC>
0x1c - Initial duty cycle for channel 1
pub fn ch2_duty(&self) -> &Reg<CH_DUTY_SPEC>
pub fn ch2_duty(&self) -> &Reg<CH_DUTY_SPEC>
0x30 - Initial duty cycle for channel 2
pub fn ch3_duty(&self) -> &Reg<CH_DUTY_SPEC>
pub fn ch3_duty(&self) -> &Reg<CH_DUTY_SPEC>
0x44 - Initial duty cycle for channel 3
pub fn ch4_duty(&self) -> &Reg<CH_DUTY_SPEC>
pub fn ch4_duty(&self) -> &Reg<CH_DUTY_SPEC>
0x58 - Initial duty cycle for channel 4
pub fn ch5_duty(&self) -> &Reg<CH_DUTY_SPEC>
pub fn ch5_duty(&self) -> &Reg<CH_DUTY_SPEC>
0x6c - Initial duty cycle for channel 5
pub fn ch6_duty(&self) -> &Reg<CH_DUTY_SPEC>
pub fn ch6_duty(&self) -> &Reg<CH_DUTY_SPEC>
0x80 - Initial duty cycle for channel 6
pub fn ch7_duty(&self) -> &Reg<CH_DUTY_SPEC>
pub fn ch7_duty(&self) -> &Reg<CH_DUTY_SPEC>
0x94 - Initial duty cycle for channel 7
pub fn ch_conf1(&self, n: usize) -> &Reg<CH_CONF1_SPEC>
pub fn ch_conf1(&self, n: usize) -> &Reg<CH_CONF1_SPEC>
0x0c..0x2c - Configuration register 1 for channel %s
pub fn ch_conf1_iter(&self) -> impl Iterator<Item = &Reg<CH_CONF1_SPEC>>
pub fn ch_conf1_iter(&self) -> impl Iterator<Item = &Reg<CH_CONF1_SPEC>>
Iterator for array of: 0x0c..0x2c - Configuration register 1 for channel %s
pub fn ch0_conf1(&self) -> &Reg<CH_CONF1_SPEC>
pub fn ch0_conf1(&self) -> &Reg<CH_CONF1_SPEC>
0x0c - Configuration register 1 for channel 0
pub fn ch1_conf1(&self) -> &Reg<CH_CONF1_SPEC>
pub fn ch1_conf1(&self) -> &Reg<CH_CONF1_SPEC>
0x20 - Configuration register 1 for channel 1
pub fn ch2_conf1(&self) -> &Reg<CH_CONF1_SPEC>
pub fn ch2_conf1(&self) -> &Reg<CH_CONF1_SPEC>
0x34 - Configuration register 1 for channel 2
pub fn ch3_conf1(&self) -> &Reg<CH_CONF1_SPEC>
pub fn ch3_conf1(&self) -> &Reg<CH_CONF1_SPEC>
0x48 - Configuration register 1 for channel 3
pub fn ch4_conf1(&self) -> &Reg<CH_CONF1_SPEC>
pub fn ch4_conf1(&self) -> &Reg<CH_CONF1_SPEC>
0x5c - Configuration register 1 for channel 4
pub fn ch5_conf1(&self) -> &Reg<CH_CONF1_SPEC>
pub fn ch5_conf1(&self) -> &Reg<CH_CONF1_SPEC>
0x70 - Configuration register 1 for channel 5
pub fn ch6_conf1(&self) -> &Reg<CH_CONF1_SPEC>
pub fn ch6_conf1(&self) -> &Reg<CH_CONF1_SPEC>
0x84 - Configuration register 1 for channel 6
pub fn ch7_conf1(&self) -> &Reg<CH_CONF1_SPEC>
pub fn ch7_conf1(&self) -> &Reg<CH_CONF1_SPEC>
0x98 - Configuration register 1 for channel 7
pub fn ch_duty_r(&self, n: usize) -> &Reg<CH_DUTY_R_SPEC>
pub fn ch_duty_r(&self, n: usize) -> &Reg<CH_DUTY_R_SPEC>
0x10..0x30 - Current duty cycle for channel %s
pub fn ch_duty_r_iter(&self) -> impl Iterator<Item = &Reg<CH_DUTY_R_SPEC>>
pub fn ch_duty_r_iter(&self) -> impl Iterator<Item = &Reg<CH_DUTY_R_SPEC>>
Iterator for array of: 0x10..0x30 - Current duty cycle for channel %s
pub fn ch0_duty_r(&self) -> &Reg<CH_DUTY_R_SPEC>
pub fn ch0_duty_r(&self) -> &Reg<CH_DUTY_R_SPEC>
0x10 - Current duty cycle for channel 0
pub fn ch1_duty_r(&self) -> &Reg<CH_DUTY_R_SPEC>
pub fn ch1_duty_r(&self) -> &Reg<CH_DUTY_R_SPEC>
0x24 - Current duty cycle for channel 1
pub fn ch2_duty_r(&self) -> &Reg<CH_DUTY_R_SPEC>
pub fn ch2_duty_r(&self) -> &Reg<CH_DUTY_R_SPEC>
0x38 - Current duty cycle for channel 2
pub fn ch3_duty_r(&self) -> &Reg<CH_DUTY_R_SPEC>
pub fn ch3_duty_r(&self) -> &Reg<CH_DUTY_R_SPEC>
0x4c - Current duty cycle for channel 3
pub fn ch4_duty_r(&self) -> &Reg<CH_DUTY_R_SPEC>
pub fn ch4_duty_r(&self) -> &Reg<CH_DUTY_R_SPEC>
0x60 - Current duty cycle for channel 4
pub fn ch5_duty_r(&self) -> &Reg<CH_DUTY_R_SPEC>
pub fn ch5_duty_r(&self) -> &Reg<CH_DUTY_R_SPEC>
0x74 - Current duty cycle for channel 5
pub fn ch6_duty_r(&self) -> &Reg<CH_DUTY_R_SPEC>
pub fn ch6_duty_r(&self) -> &Reg<CH_DUTY_R_SPEC>
0x88 - Current duty cycle for channel 6
pub fn ch7_duty_r(&self) -> &Reg<CH_DUTY_R_SPEC>
pub fn ch7_duty_r(&self) -> &Reg<CH_DUTY_R_SPEC>
0x9c - Current duty cycle for channel 7
pub fn timer_conf(&self, n: usize) -> &Reg<TIMER_CONF_SPEC>
pub fn timer_conf(&self, n: usize) -> &Reg<TIMER_CONF_SPEC>
0xa0..0xb0 - Timer %s configuration
pub fn timer_conf_iter(&self) -> impl Iterator<Item = &Reg<TIMER_CONF_SPEC>>
pub fn timer_conf_iter(&self) -> impl Iterator<Item = &Reg<TIMER_CONF_SPEC>>
Iterator for array of: 0xa0..0xb0 - Timer %s configuration
pub fn timer0_conf(&self) -> &Reg<TIMER_CONF_SPEC>
pub fn timer0_conf(&self) -> &Reg<TIMER_CONF_SPEC>
0xa0 - Timer 0 configuration
pub fn timer1_conf(&self) -> &Reg<TIMER_CONF_SPEC>
pub fn timer1_conf(&self) -> &Reg<TIMER_CONF_SPEC>
0xa8 - Timer 1 configuration
pub fn timer2_conf(&self) -> &Reg<TIMER_CONF_SPEC>
pub fn timer2_conf(&self) -> &Reg<TIMER_CONF_SPEC>
0xb0 - Timer 2 configuration
pub fn timer3_conf(&self) -> &Reg<TIMER_CONF_SPEC>
pub fn timer3_conf(&self) -> &Reg<TIMER_CONF_SPEC>
0xb8 - Timer 3 configuration
pub fn timer_value(&self, n: usize) -> &Reg<TIMER_VALUE_SPEC>
pub fn timer_value(&self, n: usize) -> &Reg<TIMER_VALUE_SPEC>
0xa4..0xb4 - Timer %s current counter value
pub fn timer_value_iter(&self) -> impl Iterator<Item = &Reg<TIMER_VALUE_SPEC>>
pub fn timer_value_iter(&self) -> impl Iterator<Item = &Reg<TIMER_VALUE_SPEC>>
Iterator for array of: 0xa4..0xb4 - Timer %s current counter value
pub fn timer0_value(&self) -> &Reg<TIMER_VALUE_SPEC>
pub fn timer0_value(&self) -> &Reg<TIMER_VALUE_SPEC>
0xa4 - Timer 0 current counter value
pub fn timer1_value(&self) -> &Reg<TIMER_VALUE_SPEC>
pub fn timer1_value(&self) -> &Reg<TIMER_VALUE_SPEC>
0xac - Timer 1 current counter value
pub fn timer2_value(&self) -> &Reg<TIMER_VALUE_SPEC>
pub fn timer2_value(&self) -> &Reg<TIMER_VALUE_SPEC>
0xb4 - Timer 2 current counter value
pub fn timer3_value(&self) -> &Reg<TIMER_VALUE_SPEC>
pub fn timer3_value(&self) -> &Reg<TIMER_VALUE_SPEC>
0xbc - Timer 3 current counter value
pub fn int_raw(&self) -> &Reg<INT_RAW_SPEC>
pub fn int_raw(&self) -> &Reg<INT_RAW_SPEC>
0xc0 - Raw interrupt status
pub fn int_st(&self) -> &Reg<INT_ST_SPEC>
pub fn int_st(&self) -> &Reg<INT_ST_SPEC>
0xc4 - Masked interrupt status
pub fn int_ena(&self) -> &Reg<INT_ENA_SPEC>
pub fn int_ena(&self) -> &Reg<INT_ENA_SPEC>
0xc8 - Interrupt enable bits
pub fn int_clr(&self) -> &Reg<INT_CLR_SPEC>
pub fn int_clr(&self) -> &Reg<INT_CLR_SPEC>
0xcc - Interrupt clear bits
pub fn conf(&self) -> &Reg<CONF_SPEC>
pub fn conf(&self) -> &Reg<CONF_SPEC>
0xd0 - Global ledc configuration register
pub fn date(&self) -> &Reg<DATE_SPEC>
pub fn date(&self) -> &Reg<DATE_SPEC>
0xfc - Version control register