esp32s2::spi0

Struct RegisterBlock

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#[repr(C)]
pub struct RegisterBlock { /* private fields */ }
Expand description

Register block

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impl RegisterBlock

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pub const fn cmd(&self) -> &CMD

0x00 - Command control register

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pub const fn addr(&self) -> &ADDR

0x04 - Address value

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pub const fn ctrl(&self) -> &CTRL

0x08 - SPI control register

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pub const fn ctrl1(&self) -> &CTRL1

0x0c - SPI control register 1

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pub const fn ctrl2(&self) -> &CTRL2

0x10 - SPI control register 2

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pub const fn clock(&self) -> &CLOCK

0x14 - SPI clock control register

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pub const fn user(&self) -> &USER

0x18 - SPI USER control register

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pub const fn user1(&self) -> &USER1

0x1c - SPI USER control register 1

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pub const fn user2(&self) -> &USER2

0x20 - SPI USER control register 2

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pub const fn mosi_dlen(&self) -> &MOSI_DLEN

0x24 - MOSI length

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pub const fn miso_dlen(&self) -> &MISO_DLEN

0x28 - MISO length

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pub const fn misc(&self) -> &MISC

0x2c - SPI misc register

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pub const fn slave(&self) -> &SLAVE

0x30 - SPI slave control register

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pub const fn slave1(&self) -> &SLAVE1

0x34 - SPI slave control register 1

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pub const fn slv_wrbuf_dlen(&self) -> &SLV_WRBUF_DLEN

0x38 - SPI slave Wr_BUF interrupt and CONF control register

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pub const fn slv_rdbuf_dlen(&self) -> &SLV_RDBUF_DLEN

0x3c - SPI magic error and slave control register

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pub const fn cache_sctrl(&self) -> &CACHE_SCTRL

0x40 - SPI Memory Cache SCTRL Register

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pub const fn slv_rd_byte(&self) -> &SLV_RD_BYTE

0x40 - SPI interrupt control register

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pub const fn fsm(&self) -> &FSM

0x44 - SPI master status and DMA read byte control register

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pub const fn sram_drd_cmd(&self) -> &SRAM_DRD_CMD

0x48 - SPI Memory SRAM DRD CMD Register

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pub const fn hold(&self) -> &HOLD

0x48 - SPI hold register

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pub const fn sram_dwr_cmd(&self) -> &SRAM_DWR_CMD

0x4c - SPI Memory SRAM DWR CMD Register

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pub const fn dma_conf(&self) -> &DMA_CONF

0x4c - SPI DMA control register

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pub const fn sram_clk(&self) -> &SRAM_CLK

0x50 - SPI Memory SRAM Clock Register

0x50 - SPI DMA TX link configuration

0x54 - SPI DMA RX link configuration

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pub const fn dma_int_ena(&self) -> &DMA_INT_ENA

0x58 - SPI DMA interrupt enable register

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pub const fn dma_int_raw(&self) -> &DMA_INT_RAW

0x5c - SPI DMA interrupt raw register

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pub const fn dma_int_st(&self) -> &DMA_INT_ST

0x60 - SPI DMA interrupt status register

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pub const fn dma_int_clr(&self) -> &DMA_INT_CLR

0x64 - SPI DMA interrupt clear register

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pub const fn in_err_eof_des_addr(&self) -> &IN_ERR_EOF_DES_ADDR

0x68 - The latest SPI DMA RX descriptor address receiving error

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pub const fn in_suc_eof_des_addr(&self) -> &IN_SUC_EOF_DES_ADDR

0x6c - The latest SPI DMA eof RX descriptor address

0x70 - Current SPI DMA RX descriptor pointer

0x74 - Next SPI DMA RX descriptor pointer

0x78 - Current SPI DMA RX buffer pointer

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pub const fn out_eof_bfr_des_addr(&self) -> &OUT_EOF_BFR_DES_ADDR

0x7c - The latest SPI DMA eof TX buffer address

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pub const fn out_eof_des_addr(&self) -> &OUT_EOF_DES_ADDR

0x80 - The latest SPI DMA eof TX descriptor address

0x84 - Current SPI DMA TX descriptor pointer

0x88 - Next SPI DMA TX descriptor pointer

0x8c - Current SPI DMA TX buffer pointer

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pub const fn dma_outstatus(&self) -> &DMA_OUTSTATUS

0x90 - SPI DMA TX status

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pub const fn dma_instatus(&self) -> &DMA_INSTATUS

0x94 - SPI DMA RX status

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pub const fn w(&self, n: usize) -> &W

0x98..0xe0 - Data buffer %s

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pub fn w_iter(&self) -> impl Iterator<Item = &W>

Iterator for array of: 0x98..0xe0 - Data buffer %s

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pub const fn clock_gate(&self) -> &CLOCK_GATE

0xdc - SPI Memory Clock Gate Register

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pub const fn din_mode(&self) -> &DIN_MODE

0xe0 - SPI input delay mode configuration

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pub const fn din_num(&self) -> &DIN_NUM

0xe4 - SPI input delay number configuration

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pub const fn dout_mode(&self) -> &DOUT_MODE

0xe8 - SPI output delay mode configuration

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pub const fn dout_num(&self) -> &DOUT_NUM

0xec - SPI output delay number configuration

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pub const fn lcd_ctrl(&self) -> &LCD_CTRL

0xf0 - LCD frame control register

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pub const fn lcd_ctrl1(&self) -> &LCD_CTRL1

0xf4 - LCD frame control1 register

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pub const fn lcd_ctrl2(&self) -> &LCD_CTRL2

0xf8 - LCD frame control2 register

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pub const fn lcd_d_mode(&self) -> &LCD_D_MODE

0xfc - LCD delay number

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pub const fn lcd_d_num(&self) -> &LCD_D_NUM

0x100 - LCD delay mode

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pub const fn reg_date(&self) -> &REG_DATE

0x3fc - SPI version control

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