Struct esp32s2::extmem::cache_dbg_status0::R

pub struct R(_);

Register CACHE_DBG_STATUS0 reader

Implementations

impl R

pub fn ibus0_acs_msk_icache_st(&self) -> IBUS0_ACS_MSK_ICACHE_ST_R

Bit 0 - The bit is used to indicate interrupt by cpu access icache while the ibus0 is disabled or icache is disabled which include speculative access.

pub fn ibus1_acs_msk_icache_st(&self) -> IBUS1_ACS_MSK_ICACHE_ST_R

Bit 1 - The bit is used to indicate interrupt by cpu access icache while the ibus1 is disabled or icache is disabled which include speculative access.

pub fn ibus2_acs_msk_icache_st(&self) -> IBUS2_ACS_MSK_ICACHE_ST_R

Bit 2 - The bit is used to indicate interrupt by cpu access icache while the ibus2 is disabled or icache is disabled which include speculative access.

pub fn ibus0_acs_cnt_ovf_st(&self) -> IBUS0_ACS_CNT_OVF_ST_R

Bit 4 - The bit is used to indicate interrupt by ibus0 counter overflow.

pub fn ibus1_acs_cnt_ovf_st(&self) -> IBUS1_ACS_CNT_OVF_ST_R

Bit 5 - The bit is used to indicate interrupt by ibus1 counter overflow.

pub fn ibus2_acs_cnt_ovf_st(&self) -> IBUS2_ACS_CNT_OVF_ST_R

Bit 6 - The bit is used to indicate interrupt by ibus2 counter overflow.

pub fn ibus0_acs_miss_cnt_ovf_st(&self) -> IBUS0_ACS_MISS_CNT_OVF_ST_R

Bit 8 - The bit is used to indicate interrupt by ibus0 miss counter overflow.

pub fn ibus1_acs_miss_cnt_ovf_st(&self) -> IBUS1_ACS_MISS_CNT_OVF_ST_R

Bit 9 - The bit is used to indicate interrupt by ibus1 miss counter overflow.

pub fn ibus2_acs_miss_cnt_ovf_st(&self) -> IBUS2_ACS_MISS_CNT_OVF_ST_R

Bit 10 - The bit is used to indicate interrupt by ibus2 miss counter overflow.

pub fn ibus0_abandon_cnt_ovf_st(&self) -> IBUS0_ABANDON_CNT_OVF_ST_R

Bit 12 - The bit is used to indicate interrupt by ibus0 abandon counter overflow.

pub fn ibus1_abandon_cnt_ovf_st(&self) -> IBUS1_ABANDON_CNT_OVF_ST_R

Bit 13 - The bit is used to indicate interrupt by ibus1 abandon counter overflow.

pub fn ibus2_abandon_cnt_ovf_st(&self) -> IBUS2_ABANDON_CNT_OVF_ST_R

Bit 14 - The bit is used to indicate interrupt by ibus2 abandon counter overflow.

pub fn ic_preload_miss_cnt_ovf_st(&self) -> IC_PRELOAD_MISS_CNT_OVF_ST_R

Bit 16 - The bit is used to indicate interrupt by pre-load miss counter overflow.

pub fn ic_preload_cnt_ovf_st(&self) -> IC_PRELOAD_CNT_OVF_ST_R

Bit 18 - The bit is used to indicate interrupt by pre-load counter overflow.

pub fn ic_sync_size_fault_st(&self) -> IC_SYNC_SIZE_FAULT_ST_R

Bit 19 - The bit is used to indicate interrupt by manual sync configurations fault.

pub fn ic_preload_size_fault_st(&self) -> IC_PRELOAD_SIZE_FAULT_ST_R

Bit 20 - The bit is used to indicate interrupt by manual pre-load configurations fault.

pub fn icache_reject_st(&self) -> ICACHE_REJECT_ST_R

Bit 21 - The bit is used to indicate interrupt by authentication fail.

pub fn icache_set_preload_ilg_st(&self) -> ICACHE_SET_PRELOAD_ILG_ST_R

Bit 22 - The bit is used to indicate interrupt by illegal writing preload registers of icache while icache is busy to issue lock,sync and pre-load operations.

pub fn icache_set_sync_ilg_st(&self) -> ICACHE_SET_SYNC_ILG_ST_R

Bit 23 - The bit is used to indicate interrupt by illegal writing sync registers of icache while icache is busy to issue lock,sync and pre-load operations.

pub fn icache_set_lock_ilg_st(&self) -> ICACHE_SET_LOCK_ILG_ST_R

Bit 24 - The bit is used to indicate interrupt by illegal writing lock registers of icache while icache is busy to issue lock,sync or pre-load operations.

Methods from Deref<Target = R<CACHE_DBG_STATUS0_SPEC>>

pub fn bits(&self) -> REG::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<CACHE_DBG_STATUS0_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl From<R<CACHE_DBG_STATUS0_SPEC>> for R

fn from(reader: R<CACHE_DBG_STATUS0_SPEC>) -> Self

Converts to this type from the input type.