Struct esp32s2::spi0::ctrl1::R

pub struct R(_);

Register CTRL1 reader

Implementations

impl R

pub fn clk_mode(&self) -> CLK_MODE_R

Bits 0:1 - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state.

pub fn clk_mode_13(&self) -> CLK_MODE_13_R

Bit 2 - {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6].

pub fn rsck_data_out(&self) -> RSCK_DATA_OUT_R

Bit 3 - It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge

pub fn w16_17_wr_ena(&self) -> W16_17_WR_ENA_R

Bit 4 - 1:SPI_BUF16~SPI_BUF17 can be written 0:SPI_BUF16~SPI_BUF17 can not be written. Can be configured in CONF state.

pub fn cs_hold_delay(&self) -> CS_HOLD_DELAY_R

Bits 14:19 - SPI cs signal is delayed by spi clock cycles. Can be configured in CONF state.

Methods from Deref<Target = R<CTRL1_SPEC>>

pub fn bits(&self) -> REG::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<CTRL1_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl From<R<CTRL1_SPEC>> for R

fn from(reader: R<CTRL1_SPEC>) -> Self

Converts to this type from the input type.