Struct esp32s2::efuse::rd_repeat_data1::R
source · pub struct R(_);
Expand description
Register RD_REPEAT_DATA1
reader
Implementations§
source§impl R
impl R
sourcepub fn vdd_spi_drefm(&self) -> VDD_SPI_DREFM_R
pub fn vdd_spi_drefm(&self) -> VDD_SPI_DREFM_R
Bits 0:1 - SPI regulator medium voltage reference.
sourcepub fn vdd_spi_drefl(&self) -> VDD_SPI_DREFL_R
pub fn vdd_spi_drefl(&self) -> VDD_SPI_DREFL_R
Bits 2:3 - SPI regulator low voltage reference.
sourcepub fn vdd_spi_xpd(&self) -> VDD_SPI_XPD_R
pub fn vdd_spi_xpd(&self) -> VDD_SPI_XPD_R
Bit 4 - If VDD_SPI_FORCE is 1, this value determines if the VDD_SPI regulator is powered on.
sourcepub fn vdd_spi_tieh(&self) -> VDD_SPI_TIEH_R
pub fn vdd_spi_tieh(&self) -> VDD_SPI_TIEH_R
Bit 5 - If VDD_SPI_FORCE is 1, determines VDD_SPI voltage. 0: VDD_SPI connects to 1.8 V LDO. 1: VDD_SPI connects to VDD_RTC_IO.
sourcepub fn vdd_spi_force(&self) -> VDD_SPI_FORCE_R
pub fn vdd_spi_force(&self) -> VDD_SPI_FORCE_R
Bit 6 - Set this bit to use XPD_VDD_PSI_REG and VDD_SPI_TIEH to configure VDD_SPI LDO.
sourcepub fn vdd_spi_en_init(&self) -> VDD_SPI_EN_INIT_R
pub fn vdd_spi_en_init(&self) -> VDD_SPI_EN_INIT_R
Bit 7 - Set SPI regulator to 0 to configure init[1:0]=0.
sourcepub fn vdd_spi_encurlim(&self) -> VDD_SPI_ENCURLIM_R
pub fn vdd_spi_encurlim(&self) -> VDD_SPI_ENCURLIM_R
Bit 8 - Set SPI regulator to 1 to enable output current limit.
sourcepub fn vdd_spi_dcurlim(&self) -> VDD_SPI_DCURLIM_R
pub fn vdd_spi_dcurlim(&self) -> VDD_SPI_DCURLIM_R
Bits 9:11 - Tunes the current limit threshold of SPI regulator when tieh=0, about 800 mA/(8+d).
sourcepub fn vdd_spi_init(&self) -> VDD_SPI_INIT_R
pub fn vdd_spi_init(&self) -> VDD_SPI_INIT_R
Bits 12:13 - Adds resistor from LDO output to ground. 0: no resistance. 1: 6 K. 2: 4 K. 3: 2 K.
sourcepub fn vdd_spi_dcap(&self) -> VDD_SPI_DCAP_R
pub fn vdd_spi_dcap(&self) -> VDD_SPI_DCAP_R
Bits 14:15 - Prevents SPI regulator from overshoot.
sourcepub fn wdt_delay_sel(&self) -> WDT_DELAY_SEL_R
pub fn wdt_delay_sel(&self) -> WDT_DELAY_SEL_R
Bits 16:17 - Selects RTC watchdog timeout threshold at startup. 0: 40,000 slow clock cycles. 1: 80,000 slow clock cycles. 2: 160,000 slow clock cycles. 3: 320,000 slow clock cycles.
sourcepub fn spi_boot_crypt_cnt(&self) -> SPI_BOOT_CRYPT_CNT_R
pub fn spi_boot_crypt_cnt(&self) -> SPI_BOOT_CRYPT_CNT_R
Bits 18:20 - Enables encryption and decryption, when an SPI boot mode is set. Feature is enabled 1 or 3 bits are set in the eFuse, disabled otherwise.
sourcepub fn secure_boot_key_revoke0(&self) -> SECURE_BOOT_KEY_REVOKE0_R
pub fn secure_boot_key_revoke0(&self) -> SECURE_BOOT_KEY_REVOKE0_R
Bit 21 - If set, revokes use of secure boot key digest 0.
sourcepub fn secure_boot_key_revoke1(&self) -> SECURE_BOOT_KEY_REVOKE1_R
pub fn secure_boot_key_revoke1(&self) -> SECURE_BOOT_KEY_REVOKE1_R
Bit 22 - If set, revokes use of secure boot key digest 1.
sourcepub fn secure_boot_key_revoke2(&self) -> SECURE_BOOT_KEY_REVOKE2_R
pub fn secure_boot_key_revoke2(&self) -> SECURE_BOOT_KEY_REVOKE2_R
Bit 23 - If set, revokes use of secure boot key digest 2.
sourcepub fn key_purpose_0(&self) -> KEY_PURPOSE_0_R
pub fn key_purpose_0(&self) -> KEY_PURPOSE_0_R
Bits 24:27 - Purpose of KEY0. Refer to Table Key Purpose Values.
sourcepub fn key_purpose_1(&self) -> KEY_PURPOSE_1_R
pub fn key_purpose_1(&self) -> KEY_PURPOSE_1_R
Bits 28:31 - Purpose of KEY1. Refer to Table Key Purpose Values.