Struct esp32s2::gpio::RegisterBlock

source · 
#[repr(C)]
pub struct RegisterBlock {
Show 36 fields
    pub bt_select: BT_SELECT,
    pub out: OUT,
    pub out_w1ts: OUT_W1TS,
    pub out_w1tc: OUT_W1TC,
    pub out1: OUT1,
    pub out1_w1ts: OUT1_W1TS,
    pub out1_w1tc: OUT1_W1TC,
    pub sdio_select: SDIO_SELECT,
    pub enable: ENABLE,
    pub enable_w1ts: ENABLE_W1TS,
    pub enable_w1tc: ENABLE_W1TC,
    pub enable1: ENABLE1,
    pub enable1_w1ts: ENABLE1_W1TS,
    pub enable1_w1tc: ENABLE1_W1TC,
    pub strap: STRAP,
    pub in_: IN,
    pub in1: IN1,
    pub status: STATUS,
    pub status_w1ts: STATUS_W1TS,
    pub status_w1tc: STATUS_W1TC,
    pub status1: STATUS1,
    pub status1_w1ts: STATUS1_W1TS,
    pub status1_w1tc: STATUS1_W1TC,
    pub pcpu_int: PCPU_INT,
    pub pcpu_nmi_int: PCPU_NMI_INT,
    pub cpusdio_int: CPUSDIO_INT,
    pub pcpu_int1: PCPU_INT1,
    pub pcpu_nmi_int1: PCPU_NMI_INT1,
    pub cpusdio_int1: CPUSDIO_INT1,
    pub pin: [PIN; 54],
    pub status_next: STATUS_NEXT,
    pub status_next1: STATUS_NEXT1,
    pub func_in_sel_cfg: [FUNC_IN_SEL_CFG; 256],
    pub func_out_sel_cfg: [FUNC_OUT_SEL_CFG; 54],
    pub clock_gate: CLOCK_GATE,
    pub reg_date: REG_DATE,
    /* private fields */

}
Expand description

Register block

Fields§

§bt_select: BT_SELECT

0x00 - GPIO bit select register

§out: OUT

0x04 - GPIO0 ~ 31 output register

§out_w1ts: OUT_W1TS

0x08 - GPIO0 ~ 31 output bit set register

§out_w1tc: OUT_W1TC

0x0c - GPIO0 ~ 31 output bit clear register

§out1: OUT1

0x10 - GPIO32 ~ 53 output register

§out1_w1ts: OUT1_W1TS

0x14 - GPIO32 ~ 53 output bit set register

§out1_w1tc: OUT1_W1TC

0x18 - GPIO32 ~ 53 output bit clear register

§sdio_select: SDIO_SELECT

0x1c - GPIO SDIO selection register

§enable: ENABLE

0x20 - GPIO0 ~ 31 output enable register

§enable_w1ts: ENABLE_W1TS

0x24 - GPIO0 ~ 31 output enable bit set register

§enable_w1tc: ENABLE_W1TC

0x28 - GPIO0 ~ 31 output enable bit clear register

§enable1: ENABLE1

0x2c - GPIO32 ~ 53 output enable register

§enable1_w1ts: ENABLE1_W1TS

0x30 - GPIO32 ~ 53 output enable bit set register

§enable1_w1tc: ENABLE1_W1TC

0x34 - GPIO32 ~ 53 output enable bit clear register

§strap: STRAP

0x38 - Bootstrap pin value register

§in_: IN

0x3c - GPIO0 ~ 31 input register

§in1: IN1

0x40 - GPIO32 ~ 53 input register

§status: STATUS

0x44 - GPIO0 ~ 31 interrupt status register

§status_w1ts: STATUS_W1TS

0x48 - GPIO0 ~ 31 interrupt status bit set register

§status_w1tc: STATUS_W1TC

0x4c - GPIO0 ~ 31 interrupt status bit clear register

§status1: STATUS1

0x50 - GPIO32 ~ 53 interrupt status register

§status1_w1ts: STATUS1_W1TS

0x54 - GPIO32 ~ 53 interrupt status bit set register

§status1_w1tc: STATUS1_W1TC

0x58 - GPIO32 ~ 53 interrupt status bit clear register

§pcpu_int: PCPU_INT

0x5c - GPIO0 ~ 31 PRO_CPU interrupt status register

§pcpu_nmi_int: PCPU_NMI_INT

0x60 - GPIO0 ~ 31 PRO_CPU non-maskable interrupt status register

§cpusdio_int: CPUSDIO_INT

0x64 - GPIO0 ~ 31 CPU SDIO interrupt status register

§pcpu_int1: PCPU_INT1

0x68 - GPIO32 ~ 53 PRO_CPU interrupt status register

§pcpu_nmi_int1: PCPU_NMI_INT1

0x6c - GPIO32 ~ 53 PRO_CPU non-maskable interrupt status register

§cpusdio_int1: CPUSDIO_INT1

0x70 - GPIO32 ~ 53 CPU SDIO interrupt status register

§pin: [PIN; 54]

0x74..0x14c - Configuration for GPIO pin %s

§status_next: STATUS_NEXT

0x14c - GPIO0 ~ 31 interrupt source register

§status_next1: STATUS_NEXT1

0x150 - GPIO32 ~ 53 interrupt source register

§func_in_sel_cfg: [FUNC_IN_SEL_CFG; 256]

0x154..0x554 - Peripheral function %s input selection register

§func_out_sel_cfg: [FUNC_OUT_SEL_CFG; 54]

0x554..0x62c - Peripheral output selection for GPIO %s

§clock_gate: CLOCK_GATE

0x62c - GPIO clock gating register

§reg_date: REG_DATE

0x6fc - Version control register

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