Expand description
UART threshold and allocation configuration
Structs
UART threshold and allocation configuration
Register
MEM_CONF readerRegister
MEM_CONF writerType Definitions
Field
MEM_FORCE_PD reader - Set this bit to force power down UART RAM.Field
MEM_FORCE_PD writer - Set this bit to force power down UART RAM.Field
MEM_FORCE_PU reader - Set this bit to force power up UART RAM.Field
MEM_FORCE_PU writer - Set this bit to force power up UART RAM.Field
RX_FLOW_THRHD reader - This register is used to configure the maximum amount of data bytes that can be received when hardware flow control works.Field
RX_FLOW_THRHD writer - This register is used to configure the maximum amount of data bytes that can be received when hardware flow control works.Field
RX_SIZE reader - This register is used to configure the amount of RAM allocated for RX FIFO. The default number is 128 bytes.Field
RX_SIZE writer - This register is used to configure the amount of RAM allocated for RX FIFO. The default number is 128 bytes.Field
RX_TOUT_THRHD reader - This register is used to configure the threshold time that the receiver takes to receive one byte, in the unit of bit time (the time it takes to transfer one bit). The UART_RXFIFO_TOUT_INT interrupt will be triggered when the receiver takes more time to receive one byte with UART RX_TOUT_EN set to 1.Field
RX_TOUT_THRHD writer - This register is used to configure the threshold time that the receiver takes to receive one byte, in the unit of bit time (the time it takes to transfer one bit). The UART_RXFIFO_TOUT_INT interrupt will be triggered when the receiver takes more time to receive one byte with UART RX_TOUT_EN set to 1.Field
TX_SIZE reader - This register is used to configure the amount of RAM allocated for TX FIFO. The default number is 128 bytes.Field
TX_SIZE writer - This register is used to configure the amount of RAM allocated for TX FIFO. The default number is 128 bytes.