Struct esp32s2::spi0::RegisterBlock
source · #[repr(C)]pub struct RegisterBlock {Show 66 fields
pub cmd: CMD,
pub addr: ADDR,
pub ctrl: CTRL,
pub ctrl1: CTRL1,
pub ctrl2: CTRL2,
pub clock: CLOCK,
pub user: USER,
pub user1: USER1,
pub user2: USER2,
pub mosi_dlen: MOSI_DLEN,
pub miso_dlen: MISO_DLEN,
pub misc: MISC,
pub slave: SLAVE,
pub slave1: SLAVE1,
pub slv_wrbuf_dlen: SLV_WRBUF_DLEN,
pub slv_rdbuf_dlen: SLV_RDBUF_DLEN,
pub slv_rd_byte: SLV_RD_BYTE,
pub fsm: FSM,
pub hold: HOLD,
pub dma_conf: DMA_CONF,
pub dma_out_link: DMA_OUT_LINK,
pub dma_in_link: DMA_IN_LINK,
pub dma_int_ena: DMA_INT_ENA,
pub dma_int_raw: DMA_INT_RAW,
pub dma_int_st: DMA_INT_ST,
pub dma_int_clr: DMA_INT_CLR,
pub in_err_eof_des_addr: IN_ERR_EOF_DES_ADDR,
pub in_suc_eof_des_addr: IN_SUC_EOF_DES_ADDR,
pub inlink_dscr: INLINK_DSCR,
pub inlink_dscr_bf0: INLINK_DSCR_BF0,
pub inlink_dscr_bf1: INLINK_DSCR_BF1,
pub out_eof_bfr_des_addr: OUT_EOF_BFR_DES_ADDR,
pub out_eof_des_addr: OUT_EOF_DES_ADDR,
pub outlink_dscr: OUTLINK_DSCR,
pub outlink_dscr_bf0: OUTLINK_DSCR_BF0,
pub outlink_dscr_bf1: OUTLINK_DSCR_BF1,
pub dma_outstatus: DMA_OUTSTATUS,
pub dma_instatus: DMA_INSTATUS,
pub w0: W0,
pub w1: W1,
pub w2: W2,
pub w3: W3,
pub w4: W4,
pub w5: W5,
pub w6: W6,
pub w7: W7,
pub w8: W8,
pub w9: W9,
pub w10: W10,
pub w11: W11,
pub w12: W12,
pub w13: W13,
pub w14: W14,
pub w15: W15,
pub w16: W16,
pub w17: W17,
pub din_mode: DIN_MODE,
pub din_num: DIN_NUM,
pub dout_mode: DOUT_MODE,
pub dout_num: DOUT_NUM,
pub lcd_ctrl: LCD_CTRL,
pub lcd_ctrl1: LCD_CTRL1,
pub lcd_ctrl2: LCD_CTRL2,
pub lcd_d_mode: LCD_D_MODE,
pub lcd_d_num: LCD_D_NUM,
pub reg_date: REG_DATE,
/* private fields */
}Expand description
Register block
Fields
cmd: CMD0x00 - Command control register
addr: ADDR0x04 - Address value
ctrl: CTRL0x08 - SPI control register
ctrl1: CTRL10x0c - SPI control register 1
ctrl2: CTRL20x10 - SPI control register 2
clock: CLOCK0x14 - SPI clock control register
user: USER0x18 - SPI USER control register
user1: USER10x1c - SPI USER control register 1
user2: USER20x20 - SPI USER control register 2
mosi_dlen: MOSI_DLEN0x24 - MOSI length
miso_dlen: MISO_DLEN0x28 - MISO length
misc: MISC0x2c - SPI misc register
slave: SLAVE0x30 - SPI slave control register
slave1: SLAVE10x34 - SPI slave control register 1
slv_wrbuf_dlen: SLV_WRBUF_DLEN0x38 - SPI slave Wr_BUF interrupt and CONF control register
slv_rdbuf_dlen: SLV_RDBUF_DLEN0x3c - SPI magic error and slave control register
slv_rd_byte: SLV_RD_BYTE0x40 - SPI interrupt control register
fsm: FSM0x44 - SPI master status and DMA read byte control register
hold: HOLD0x48 - SPI hold register
dma_conf: DMA_CONF0x4c - SPI DMA control register
dma_out_link: DMA_OUT_LINK0x50 - SPI DMA TX link configuration
dma_in_link: DMA_IN_LINK0x54 - SPI DMA RX link configuration
dma_int_ena: DMA_INT_ENA0x58 - SPI DMA interrupt enable register
dma_int_raw: DMA_INT_RAW0x5c - SPI DMA interrupt raw register
dma_int_st: DMA_INT_ST0x60 - SPI DMA interrupt status register
dma_int_clr: DMA_INT_CLR0x64 - SPI DMA interrupt clear register
in_err_eof_des_addr: IN_ERR_EOF_DES_ADDR0x68 - The latest SPI DMA RX descriptor address receiving error
in_suc_eof_des_addr: IN_SUC_EOF_DES_ADDR0x6c - The latest SPI DMA eof RX descriptor address
inlink_dscr: INLINK_DSCR0x70 - Current SPI DMA RX descriptor pointer
inlink_dscr_bf0: INLINK_DSCR_BF00x74 - Next SPI DMA RX descriptor pointer
inlink_dscr_bf1: INLINK_DSCR_BF10x78 - Current SPI DMA RX buffer pointer
out_eof_bfr_des_addr: OUT_EOF_BFR_DES_ADDR0x7c - The latest SPI DMA eof TX buffer address
out_eof_des_addr: OUT_EOF_DES_ADDR0x80 - The latest SPI DMA eof TX descriptor address
outlink_dscr: OUTLINK_DSCR0x84 - Current SPI DMA TX descriptor pointer
outlink_dscr_bf0: OUTLINK_DSCR_BF00x88 - Next SPI DMA TX descriptor pointer
outlink_dscr_bf1: OUTLINK_DSCR_BF10x8c - Current SPI DMA TX buffer pointer
dma_outstatus: DMA_OUTSTATUS0x90 - SPI DMA TX status
dma_instatus: DMA_INSTATUS0x94 - SPI DMA RX status
w0: W00x98 - Data buffer 0
w1: W10x9c - Data buffer 1
w2: W20xa0 - Data buffer 2
w3: W30xa4 - Data buffer 3
w4: W40xa8 - Data buffer 4
w5: W50xac - Data buffer 5
w6: W60xb0 - Data buffer 6
w7: W70xb4 - Data buffer 7
w8: W80xb8 - Data buffer 8
w9: W90xbc - Data buffer 9
w10: W100xc0 - Data buffer 10
w11: W110xc4 - Data buffer 11
w12: W120xc8 - Data buffer 12
w13: W130xcc - Data buffer 13
w14: W140xd0 - Data buffer 14
w15: W150xd4 - Data buffer 15
w16: W160xd8 - Data buffer 16
w17: W170xdc - Data buffer 17
din_mode: DIN_MODE0xe0 - SPI input delay mode configuration
din_num: DIN_NUM0xe4 - SPI input delay number configuration
dout_mode: DOUT_MODE0xe8 - SPI output delay mode configuration
dout_num: DOUT_NUM0xec - SPI output delay number configuration
lcd_ctrl: LCD_CTRL0xf0 - LCD frame control register
lcd_ctrl1: LCD_CTRL10xf4 - LCD frame control1 register
lcd_ctrl2: LCD_CTRL20xf8 - LCD frame control2 register
lcd_d_mode: LCD_D_MODE0xfc - LCD delay number
lcd_d_num: LCD_D_NUM0x100 - LCD delay mode
reg_date: REG_DATE0x3fc - SPI version control