Struct esp32s2::rtc_cntl::cocpu_ctrl::W

pub struct W(_);

Register COCPU_CTRL writer

Implementations

impl W

pub fn cocpu_clk_fo(&mut self) -> COCPU_CLK_FO_W<'_, 0>

Bit 0 - ULP-RISCV clock force on

pub fn cocpu_start_2_reset_dis(&mut self) -> COCPU_START_2_RESET_DIS_W<'_, 1>

Bits 1:6 - Time from ULP-RISCV startup to pull down reset

pub fn cocpu_start_2_intr_en(&mut self) -> COCPU_START_2_INTR_EN_W<'_, 7>

Bits 7:12 - Time from ULP-RISCV startup to send out RISCV_START_INT interrupt

pub fn cocpu_shut(&mut self) -> COCPU_SHUT_W<'_, 13>

Bit 13 - Shut down ULP-RISCV

pub fn cocpu_shut_2_clk_dis(&mut self) -> COCPU_SHUT_2_CLK_DIS_W<'_, 14>

Bits 14:21 - Time from shut down ULP-RISCV to disable clock

pub fn cocpu_shut_reset_en(&mut self) -> COCPU_SHUT_RESET_EN_W<'_, 22>

Bit 22 - This bit is used to reset ULP-RISCV

pub fn cocpu_sel(&mut self) -> COCPU_SEL_W<'_, 23>

Bit 23 - 0: select ULP-RISCV. 1: select ULP-FSM

pub fn cocpu_done_force(&mut self) -> COCPU_DONE_FORCE_W<'_, 24>

Bit 24 - 0: select ULP-FSM DONE signal. 1: select ULP-RISCV DONE signal

pub fn cocpu_done(&mut self) -> COCPU_DONE_W<'_, 25>

Bit 25 - DONE signal. Write 1 to this bit, ULP-RISCV will go to HALT and the timer starts counting

pub fn cocpu_sw_int_trigger(&mut self) -> COCPU_SW_INT_TRIGGER_W<'_, 26>

Bit 26 - Trigger ULP-RISCV register interrupt

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Methods from Deref<Target = W<COCPU_CTRL_SPEC>>

pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self

Writes raw bits to the register.

Safety

Read datasheet or reference manual to find what values are allowed to pass.

Trait Implementations

impl Deref for W

type Target = W<COCPU_CTRL_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut Self::Target

Mutably dereferences the value.

impl From<W<COCPU_CTRL_SPEC>> for W

fn from(writer: W<COCPU_CTRL_SPEC>) -> Self

Converts to this type from the input type.