Struct esp32s2::spi0::user::W

pub struct W(_);

Register USER writer

Implementations

impl W

pub fn doutdin(&mut self) -> DOUTDIN_W<'_, 0>

Bit 0 - Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state.

pub fn qpi_mode(&mut self) -> QPI_MODE_W<'_, 3>

Bit 3 - Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state.

pub fn opi_mode(&mut self) -> OPI_MODE_W<'_, 4>

Bit 4 - Just for master mode. 1: spi controller is in OPI mode (all in 8-bit mode). 0: others. Can be configured in CONF state.

pub fn tsck_i_edge(&mut self) -> TSCK_I_EDGE_W<'_, 5>

Bit 5 - In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i.

pub fn cs_hold(&mut self) -> CS_HOLD_W<'_, 6>

Bit 6 - spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state.

pub fn cs_setup(&mut self) -> CS_SETUP_W<'_, 7>

Bit 7 - spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state.

pub fn rsck_i_edge(&mut self) -> RSCK_I_EDGE_W<'_, 8>

Bit 8 - In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i.

pub fn ck_out_edge(&mut self) -> CK_OUT_EDGE_W<'_, 9>

Bit 9 - the bit combined with SPI_DOUT_MODE register to set mosi signal delay mode. Can be configured in CONF state.

pub fn rd_byte_order(&mut self) -> RD_BYTE_ORDER_W<'_, 10>

Bit 10 - In read-data (MISO) phase 1: big-endian 0: little_endian. Can be configured in CONF state.

pub fn wr_byte_order(&mut self) -> WR_BYTE_ORDER_W<'_, 11>

Bit 11 - In command address write-data (MOSI) phases 1: big-endian 0: litte_endian. Can be configured in CONF state.

pub fn fwrite_dual(&mut self) -> FWRITE_DUAL_W<'_, 12>

Bit 12 - In the write operations read-data phase is in 2-bit mode. Can be configured in CONF state.

pub fn fwrite_quad(&mut self) -> FWRITE_QUAD_W<'_, 13>

Bit 13 - In the write operations read-data phase is in 4-bit mode. Can be configured in CONF state.

pub fn fwrite_oct(&mut self) -> FWRITE_OCT_W<'_, 14>

Bit 14 - In the write operations read-data phase is in 8-bit mode. Can be configured in CONF state.

pub fn usr_conf_nxt(&mut self) -> USR_CONF_NXT_W<'_, 15>

Bit 15 - 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state.

pub fn sio(&mut self) -> SIO_W<'_, 16>

Bit 16 - Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state.

pub fn usr_hold_pol(&mut self) -> USR_HOLD_POL_W<'_, 17>

Bit 17 - It is combined with hold bits to set the polarity of spi hold line 1: spi will be held when spi hold line is high 0: spi will be held when spi hold line is low. Can be configured in CONF state.

pub fn usr_dout_hold(&mut self) -> USR_DOUT_HOLD_W<'_, 18>

Bit 18 - spi is hold at data out state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state.

pub fn usr_din_hold(&mut self) -> USR_DIN_HOLD_W<'_, 19>

Bit 19 - spi is hold at data in state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state.

pub fn usr_dummy_hold(&mut self) -> USR_DUMMY_HOLD_W<'_, 20>

Bit 20 - spi is hold at dummy state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state.

pub fn usr_addr_hold(&mut self) -> USR_ADDR_HOLD_W<'_, 21>

Bit 21 - spi is hold at address state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state.

pub fn usr_cmd_hold(&mut self) -> USR_CMD_HOLD_W<'_, 22>

Bit 22 - spi is hold at command state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state.

pub fn usr_prep_hold(&mut self) -> USR_PREP_HOLD_W<'_, 23>

Bit 23 - spi is hold at prepare state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state.

pub fn usr_miso_highpart(&mut self) -> USR_MISO_HIGHPART_W<'_, 24>

Bit 24 - read-data phase only access to high-part of the buffer SPI_BUF8~SPI_BUF17. 1: enable 0: disable. Can be configured in CONF state.

pub fn usr_mosi_highpart(&mut self) -> USR_MOSI_HIGHPART_W<'_, 25>

Bit 25 - write-data phase only access to high-part of the buffer SPI_BUF8~SPI_BUF17. 1: enable 0: disable. Can be configured in CONF state.

pub fn usr_dummy_idle(&mut self) -> USR_DUMMY_IDLE_W<'_, 26>

Bit 26 - spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state.

pub fn usr_mosi(&mut self) -> USR_MOSI_W<'_, 27>

Bit 27 - This bit enable the write-data phase of an operation. Can be configured in CONF state.

pub fn usr_miso(&mut self) -> USR_MISO_W<'_, 28>

Bit 28 - This bit enable the read-data phase of an operation. Can be configured in CONF state.

pub fn usr_dummy(&mut self) -> USR_DUMMY_W<'_, 29>

Bit 29 - This bit enable the dummy phase of an operation. Can be configured in CONF state.

pub fn usr_addr(&mut self) -> USR_ADDR_W<'_, 30>

Bit 30 - This bit enable the address phase of an operation. Can be configured in CONF state.

pub fn usr_command(&mut self) -> USR_COMMAND_W<'_, 31>

Bit 31 - This bit enable the command phase of an operation. Can be configured in CONF state.

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Methods from Deref<Target = W<USER_SPEC>>

pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self

Writes raw bits to the register.

Safety

Read datasheet or reference manual to find what values are allowed to pass.

Trait Implementations

impl Deref for W

type Target = W<USER_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut Self::Target

Mutably dereferences the value.

impl From<W<USER_SPEC>> for W

fn from(writer: W<USER_SPEC>) -> Self

Converts to this type from the input type.