Struct esp32s2::spi0::misc::W

pub struct W(_);

Register MISC writer

Implementations

impl W

pub fn cs0_dis(&mut self) -> CS0_DIS_W<'_, 0>

Bit 0 - SPI CS0 pin enable, 1: disable CS0, 0: SPI_CS0 signal is from/to CS0 pin. Can be configured in CONF state.

pub fn cs1_dis(&mut self) -> CS1_DIS_W<'_, 1>

Bit 1 - SPI CS1 pin enable, 1: disable CS1, 0: SPI_CS1 signal is from/to CS1 pin. Can be configured in CONF state.

pub fn cs2_dis(&mut self) -> CS2_DIS_W<'_, 2>

Bit 2 - SPI CS2 pin enable, 1: disable CS2, 0: SPI_CS2 signal is from/to CS2 pin. Can be configured in CONF state.

pub fn cs3_dis(&mut self) -> CS3_DIS_W<'_, 3>

Bit 3 - SPI CS3 pin enable, 1: disable CS3, 0: SPI_CS3 signal is from/to CS3 pin. Can be configured in CONF state.

pub fn cs4_dis(&mut self) -> CS4_DIS_W<'_, 4>

Bit 4 - SPI CS4 pin enable, 1: disable CS4, 0: SPI_CS4 signal is from/to CS4 pin. Can be configured in CONF state.

pub fn cs5_dis(&mut self) -> CS5_DIS_W<'_, 5>

Bit 5 - SPI CS5 pin enable, 1: disable CS5, 0: SPI_CS5 signal is from/to CS5 pin. Can be configured in CONF state.

pub fn ck_dis(&mut self) -> CK_DIS_W<'_, 6>

Bit 6 - 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state.

pub fn master_cs_pol(&mut self) -> MASTER_CS_POL_W<'_, 7>

Bits 7:12 - In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ SPI_MASTER_CS_POL. Can be configured in CONF state.

pub fn clk_data_dtr_en(&mut self) -> CLK_DATA_DTR_EN_W<'_, 16>

Bit 16 - 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR mode is only applied to spi_dqs. This bit should be used with bit 17/18/19.

pub fn data_dtr_en(&mut self) -> DATA_DTR_EN_W<'_, 17>

Bit 17 - 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state.

pub fn addr_dtr_en(&mut self) -> ADDR_DTR_EN_W<'_, 18>

Bit 18 - 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state.

pub fn cmd_dtr_en(&mut self) -> CMD_DTR_EN_W<'_, 19>

Bit 19 - 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state.

pub fn cd_data_set(&mut self) -> CD_DATA_SET_W<'_, 20>

Bit 20 - 1: spi_cd = !SPI_CD_IDLE_EDGE when SPI_ST[3:0] is in SPI_DOUT or SPI_DIN state. 0: spi_cd = SPI_CD_IDLE_EDGE. Can be configured in CONF state.

pub fn cd_dummy_set(&mut self) -> CD_DUMMY_SET_W<'_, 21>

Bit 21 - 1: spi_cd = !SPI_CD_IDLE_EDGE when SPI_ST[3:0] is in SPI_DUMMY state. 0: spi_cd = SPI_CD_IDLE_EDGE. Can be configured in CONF state.

pub fn cd_addr_set(&mut self) -> CD_ADDR_SET_W<'_, 22>

Bit 22 - 1: spi_cd = !SPI_CD_IDLE_EDGE when SPI_ST[3:0] is in SPI_SEND_ADDR state. 0: spi_cd = SPI_CD_IDLE_EDGE. Can be configured in CONF state.

pub fn slave_cs_pol(&mut self) -> SLAVE_CS_POL_W<'_, 23>

Bit 23 - spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state.

pub fn dqs_idle_edge(&mut self) -> DQS_IDLE_EDGE_W<'_, 24>

Bit 24 - The default value of spi_dqs. Can be configured in CONF state.

pub fn cd_cmd_set(&mut self) -> CD_CMD_SET_W<'_, 25>

Bit 25 - 1: spi_cd = !SPI_CD_IDLE_EDGE when SPI_ST[3:0] is in SPI_SEND_CMD state. 0: spi_cd = SPI_CD_IDLE_EDGE. Can be configured in CONF state.

pub fn cd_idle_edge(&mut self) -> CD_IDLE_EDGE_W<'_, 26>

Bit 26 - The default value of spi_cd. Can be configured in CONF state.

pub fn ck_idle_edge(&mut self) -> CK_IDLE_EDGE_W<'_, 29>

Bit 29 - 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state.

pub fn cs_keep_active(&mut self) -> CS_KEEP_ACTIVE_W<'_, 30>

Bit 30 - spi cs line keep low when the bit is set. Can be configured in CONF state.

pub fn quad_din_pin_swap(&mut self) -> QUAD_DIN_PIN_SWAP_W<'_, 31>

Bit 31 - 1: spi quad input swap enable 0: spi quad input swap disable. Can be configured in CONF state.

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Methods from Deref<Target = W<MISC_SPEC>>

pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self

Writes raw bits to the register.

Safety

Read datasheet or reference manual to find what values are allowed to pass.

Trait Implementations

impl Deref for W

type Target = W<MISC_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut Self::Target

Mutably dereferences the value.

impl From<W<MISC_SPEC>> for W

fn from(writer: W<MISC_SPEC>) -> Self

Converts to this type from the input type.