Struct esp32s2::i2s::timing::W

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pub struct W(_);

Expand description

Register TIMING writer

Implementations

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impl W

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pub fn tx_bck_in_delay(&mut self) -> TX_BCK_IN_DELAY_W<'_, 0>

Bits 0:1 - Number of delay cycles for BCK signal into the transmitter based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles.

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pub fn tx_ws_in_delay(&mut self) -> TX_WS_IN_DELAY_W<'_, 2>

Bits 2:3 - Number of delay cycles for WS signal into the transmitter based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles.

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pub fn rx_bck_in_delay(&mut self) -> RX_BCK_IN_DELAY_W<'_, 4>

Bits 4:5 - Number of delay cycles for BCK signal into the receiver based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles.

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pub fn rx_ws_in_delay(&mut self) -> RX_WS_IN_DELAY_W<'_, 6>

Bits 6:7 - Number of delay cycles for WS signal into the receiver based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles.

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pub fn rx_sd_in_delay(&mut self) -> RX_SD_IN_DELAY_W<'_, 8>

Bits 8:9 - Number of delay cycles for SD signal into the receiver based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles.

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pub fn tx_bck_out_delay(&mut self) -> TX_BCK_OUT_DELAY_W<'_, 10>

Bits 10:11 - Number of delay cycles for BCK signal out of the transmitter based on I2S0_CLK. 0: delayed by 0 cycle. 1: delayed by 1 cycle. 2: delayed by 2 cycles. 3: delayed by 3 cycles.

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pub fn tx_ws_out_delay(&mut self) -> TX_WS_OUT_DELAY_W<'_, 12>

Bits 12:13 - Number of delay cycles for WS signal out of the transmitter based on I2S0_CLK. 0: delayed by 0 cycle. 1: delayed by 1 cycle. 2: delayed by 2 cycles. 3: delayed by 3 cycles.

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pub fn tx_sd_out_delay(&mut self) -> TX_SD_OUT_DELAY_W<'_, 14>

Bits 14:15 - Number of delay cycles for SD signal out of the transmitter based on I2S0_CLK. 0: delayed by 0 cycle. 1: delayed by 1 cycle. 2: delayed by 2 cycles. 3: delayed by 3 cycles.

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pub fn rx_ws_out_delay(&mut self) -> RX_WS_OUT_DELAY_W<'_, 16>

Bits 16:17 - Number of delay cycles for WS signal out of the receiver based on I2S0_CLK. 0: delayed by 0 cycle. 1: delayed by 1 cycle. 2: delayed by 2 cycles. 3: delayed by 3 cycles.

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pub fn rx_bck_out_delay(&mut self) -> RX_BCK_OUT_DELAY_W<'_, 18>

Bits 18:19 - Number of delay cycles for BCK signal out of the receiver based on I2S0_CLK. 0: delayed by 0 cycle. 1: delayed by 1 cycle. 2: delayed by 2 cycles. 3: delayed by 3 cycles.

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pub fn tx_dsync_sw(&mut self) -> TX_DSYNC_SW_W<'_, 20>

Bit 20 - Set this bit to synchronize signals into the transmitter by two flip-flop synchronizer. 0: the signals will be firstly clocked by rising clock edge , then clocked by falling clock edge. 1: the signals will be firstly clocked by falling clock edge, then clocked by rising clock edge.

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pub fn rx_dsync_sw(&mut self) -> RX_DSYNC_SW_W<'_, 21>

Bit 21 - Set this bit to synchronize signals into the receiver by two flip-flop synchronizer. 0: the signals will be clocked by rising clock edge firstly, then clocked by falling clock edge. 1: the signals will be clocked by falling clock edge firstly, then clocked by rising clock edge.

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pub fn data_enable_delay(&mut self) -> DATA_ENABLE_DELAY_W<'_, 22>

Bits 22:23 - Number of delay cycles for data valid flag based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles.

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