Expand description
Configuration register 1
Structs
Type Definitions
Field
RXFIFO_FULL_THRHD
reader - An UART_RXFIFO_FULL_INT interrupt is generated when the receiver receives more data than this register’s value.Field
RXFIFO_FULL_THRHD
writer - An UART_RXFIFO_FULL_INT interrupt is generated when the receiver receives more data than this register’s value.Field
RX_FLOW_EN
reader - This is the flow enable bit for UART receiver. 1: Choose software flow control with configuring sw_rts signal. 0: Disable software flow control.Field
RX_FLOW_EN
writer - This is the flow enable bit for UART receiver. 1: Choose software flow control with configuring sw_rts signal. 0: Disable software flow control.Field
RX_TOUT_EN
reader - This is the enable bit for UART receiver’s timeout function.Field
RX_TOUT_EN
writer - This is the enable bit for UART receiver’s timeout function.Field
RX_TOUT_FLOW_DIS
reader - Set this bit to stop accumulating idle_cnt when hardware flow control works.Field
RX_TOUT_FLOW_DIS
writer - Set this bit to stop accumulating idle_cnt when hardware flow control works.Field
TXFIFO_EMPTY_THRHD
reader - An UART_TXFIFO_EMPTY_INT interrupt is generated when the number of data bytes in TX FIFO is less than this register’s value.Field
TXFIFO_EMPTY_THRHD
writer - An UART_TXFIFO_EMPTY_INT interrupt is generated when the number of data bytes in TX FIFO is less than this register’s value.