Module esp32s2::gpio::pin

Configuration for GPIO pin %s

Structs

PIN_SPEC

Configuration for GPIO pin %s

R

Register PIN%s reader

W

Register PIN%s writer

Type Definitions

PIN_CONFIG_R

Field PIN_CONFIG reader - Reserved

PIN_CONFIG_W

Field PIN_CONFIG writer - Reserved

PIN_INT_ENA_R

Field PIN_INT_ENA reader - Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU non-maskable interrupt enabled.

PIN_INT_ENA_W

Field PIN_INT_ENA writer - Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU non-maskable interrupt enabled.

PIN_INT_TYPE_R

Field PIN_INT_TYPE reader - Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level trigger; 5: high level trigger. (R/W)

PIN_INT_TYPE_W

Field PIN_INT_TYPE writer - Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level trigger; 5: high level trigger. (R/W)

PIN_PAD_DRIVER_R

Field PIN_PAD_DRIVER reader - Pad driver selection. 0: normal output; 1: open drain output..

PIN_PAD_DRIVER_W

Field PIN_PAD_DRIVER writer - Pad driver selection. 0: normal output; 1: open drain output..

PIN_SYNC1_BYPASS_R

Field PIN_SYNC1_BYPASS reader - For the first stage synchronization, GPIO input data can be synchro- nized on either edge of the APB clock. 0: no synchronization; 1: synchronized on falling edge; 2 and 3: synchronized on rising edge.

PIN_SYNC1_BYPASS_W

Field PIN_SYNC1_BYPASS writer - For the first stage synchronization, GPIO input data can be synchro- nized on either edge of the APB clock. 0: no synchronization; 1: synchronized on falling edge; 2 and 3: synchronized on rising edge.

PIN_SYNC2_BYPASS_R

Field PIN_SYNC2_BYPASS reader - For the second stage synchronization, GPIO input data can be syn- chronized on either edge of the APB clock. 0: no synchronization; 1: synchronized on falling edge; 2 and 3: synchronized on rising edge.

PIN_SYNC2_BYPASS_W

Field PIN_SYNC2_BYPASS writer - For the second stage synchronization, GPIO input data can be syn- chronized on either edge of the APB clock. 0: no synchronization; 1: synchronized on falling edge; 2 and 3: synchronized on rising edge.

PIN_WAKEUP_ENABLE_R

Field PIN_WAKEUP_ENABLE reader - GPIO wake-up enable bit, only wakes up the CPU from Light-sleep.

PIN_WAKEUP_ENABLE_W

Field PIN_WAKEUP_ENABLE writer - GPIO wake-up enable bit, only wakes up the CPU from Light-sleep.