pub struct W(_);
Expand description

Register CONF0 writer

Implementations

Bit 0 - This register is used to configure the parity check mode. 0: even. 1: odd.

Bit 1 - Set this bit to enable UART parity check.

Bits 2:3 - This register is used to set the length of data. 0: 5 bits. 1: 6 bits. 2: 7 bits. 3: 8 bits.

Bits 4:5 - This register is used to set the length of stop bit. 1: 1 bit. 2: 1.5 bits. 3: 2 bits.

Bit 6 - This register is used to configure the software RTS signal which is used in software flow control.

Bit 7 - This register is used to configure the software DTR signal which is used in software flow control.

Bit 8 - Set this bit to enable the transmitter to send NULL characters when the process of sending data is done.

Bit 9 - Set this bit to enable IrDA loopback mode.

Bit 10 - This is the start enable bit for IrDA transmitter.

Bit 11 - 1: The IrDA transmitter’s 11th bit is the same as 10th bit. 0: Set IrDA transmitter’s 11th bit to 0.

Bit 12 - Set this bit to invert the level of IrDA transmitter.

Bit 13 - Set this bit to invert the level of IrDA receiver.

Bit 14 - Set this bit to enable UART loopback test mode.

Bit 15 - Set this bit to enable flow control function for the transmitter.

Bit 16 - Set this bit to enable IrDA protocol.

Bit 17 - Set this bit to reset the UART RX FIFO.

Bit 18 - Set this bit to reset the UART TX FIFO.

Bit 19 - Set this bit to invert the level of UART RXD signal.

Bit 20 - Set this bit to invert the level of UART CTS signal.

Bit 21 - Set this bit to invert the level of UART DSR signal.

Bit 22 - Set this bit to invert the level of UART TXD signal.

Bit 23 - Set this bit to invert the level of UART RTS signal.

Bit 24 - Set this bit to invert the level of UART DTR signal.

Bit 25 - 1: Force clock on for registers. 0: Support clock only when application writes registers.

Bit 26 - 1: The receiver stops storing data into FIFO when data is wrong. 0: The receiver stores the data even if the received data is wrong.

Bit 27 - This register is used to select the clock. 1: APB_CLK. 0: REF_TICK.

Bit 28 - The signal to enable UART RAM clock gating. 1: UART RAM powers on, the data of which can be read and written. 0: UART RAM powers down.

Writes raw bits to the register.

Methods from Deref<Target = W<CONF0_SPEC>>

Writes raw bits to the register.

Trait Implementations

The resulting type after dereferencing.

Dereferences the value.

Mutably dereferences the value.

Converts to this type from the input type.

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Mutably borrows from an owned value. Read more

Returns the argument unchanged.

Calls U::from(self).

That is, this conversion is whatever the implementation of From<T> for U chooses to do.

The type returned in the event of a conversion error.

Performs the conversion.

The type returned in the event of a conversion error.

Performs the conversion.