1#[doc = "Register `CTRL` reader"]
2pub type R = crate::R<CTRL_SPEC>;
3#[doc = "Register `CTRL` writer"]
4pub type W = crate::W<CTRL_SPEC>;
5#[doc = "Field `EXT_HOLD_EN` reader - Set the bit to hold spi. The bit is combined with SPI_USR_PREP_HOLD,SPI_USR_CMD_HOLD,SPI_USR_ADDR_HOLD,SPI_USR_DUMMY_HOLD,SPI_USR_DIN_HOLD,SPI_USR_DOUT_HOLD and SPI_USR_HOLD_POL. Can be configured in CONF state."]
6pub type EXT_HOLD_EN_R = crate::BitReader;
7#[doc = "Field `EXT_HOLD_EN` writer - Set the bit to hold spi. The bit is combined with SPI_USR_PREP_HOLD,SPI_USR_CMD_HOLD,SPI_USR_ADDR_HOLD,SPI_USR_DUMMY_HOLD,SPI_USR_DIN_HOLD,SPI_USR_DOUT_HOLD and SPI_USR_HOLD_POL. Can be configured in CONF state."]
8pub type EXT_HOLD_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `DUMMY_OUT` reader - In the dummy phase the signal level of spi is output by the spi controller. Can be configured in CONF state."]
10pub type DUMMY_OUT_R = crate::BitReader;
11#[doc = "Field `DUMMY_OUT` writer - In the dummy phase the signal level of spi is output by the spi controller. Can be configured in CONF state."]
12pub type DUMMY_OUT_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `FADDR_DUAL` reader - Apply 2-bit mode during addr phase 1:enable 0: disable. Can be configured in CONF state."]
14pub type FADDR_DUAL_R = crate::BitReader;
15#[doc = "Field `FADDR_DUAL` writer - Apply 2-bit mode during addr phase 1:enable 0: disable. Can be configured in CONF state."]
16pub type FADDR_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `FADDR_QUAD` reader - Apply 4-bit mode during addr phase 1:enable 0: disable. Can be configured in CONF state."]
18pub type FADDR_QUAD_R = crate::BitReader;
19#[doc = "Field `FADDR_QUAD` writer - Apply 4-bit mode during addr phase 1:enable 0: disable. Can be configured in CONF state."]
20pub type FADDR_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `FADDR_OCT` reader - Apply 8-bit mode during addr phase 1:enable 0: disable. Can be configured in CONF state."]
22pub type FADDR_OCT_R = crate::BitReader;
23#[doc = "Field `FADDR_OCT` writer - Apply 8-bit mode during addr phase 1:enable 0: disable. Can be configured in CONF state."]
24pub type FADDR_OCT_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `FCMD_DUAL` reader - Apply 2-bit mode during command phase 1:enable 0: disable. Can be configured in CONF state."]
26pub type FCMD_DUAL_R = crate::BitReader;
27#[doc = "Field `FCMD_DUAL` writer - Apply 2-bit mode during command phase 1:enable 0: disable. Can be configured in CONF state."]
28pub type FCMD_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `FCMD_QUAD` reader - Apply 4-bit mode during command phase 1:enable 0: disable. Can be configured in CONF state."]
30pub type FCMD_QUAD_R = crate::BitReader;
31#[doc = "Field `FCMD_QUAD` writer - Apply 4-bit mode during command phase 1:enable 0: disable. Can be configured in CONF state."]
32pub type FCMD_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `FCMD_OCT` reader - Apply 8-bit mode during command phase 1:enable 0: disable. Can be configured in CONF state."]
34pub type FCMD_OCT_R = crate::BitReader;
35#[doc = "Field `FCMD_OCT` writer - Apply 8-bit mode during command phase 1:enable 0: disable. Can be configured in CONF state."]
36pub type FCMD_OCT_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `FREAD_DUAL` reader - In the read operations, read-data phase is in 2-bit mode. 1: enable 0: disable. Can be configured in CONF state."]
38pub type FREAD_DUAL_R = crate::BitReader;
39#[doc = "Field `FREAD_DUAL` writer - In the read operations, read-data phase is in 2-bit mode. 1: enable 0: disable. Can be configured in CONF state."]
40pub type FREAD_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `FREAD_QUAD` reader - In the read operations read-data phase is in 4-bit mode. 1: enable 0: disable. Can be configured in CONF state."]
42pub type FREAD_QUAD_R = crate::BitReader;
43#[doc = "Field `FREAD_QUAD` writer - In the read operations read-data phase is in 4-bit mode. 1: enable 0: disable. Can be configured in CONF state."]
44pub type FREAD_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `FREAD_OCT` reader - In the read operations read-data phase is in 8-bit mode. 1: enable 0: disable. Can be configured in CONF state."]
46pub type FREAD_OCT_R = crate::BitReader;
47#[doc = "Field `FREAD_OCT` writer - In the read operations read-data phase is in 8-bit mode. 1: enable 0: disable. Can be configured in CONF state."]
48pub type FREAD_OCT_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `Q_POL` reader - The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state."]
50pub type Q_POL_R = crate::BitReader;
51#[doc = "Field `Q_POL` writer - The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state."]
52pub type Q_POL_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `D_POL` reader - The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state."]
54pub type D_POL_R = crate::BitReader;
55#[doc = "Field `D_POL` writer - The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state."]
56pub type D_POL_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `WP` reader - Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state."]
58pub type WP_R = crate::BitReader;
59#[doc = "Field `WP` writer - Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state."]
60pub type WP_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `RD_BIT_ORDER` reader - In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state."]
62pub type RD_BIT_ORDER_R = crate::BitReader;
63#[doc = "Field `RD_BIT_ORDER` writer - In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state."]
64pub type RD_BIT_ORDER_W<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `WR_BIT_ORDER` reader - In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state."]
66pub type WR_BIT_ORDER_R = crate::BitReader;
67#[doc = "Field `WR_BIT_ORDER` writer - In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state."]
68pub type WR_BIT_ORDER_W<'a, REG> = crate::BitWriter<'a, REG>;
69impl R {
70 #[doc = "Bit 2 - Set the bit to hold spi. The bit is combined with SPI_USR_PREP_HOLD,SPI_USR_CMD_HOLD,SPI_USR_ADDR_HOLD,SPI_USR_DUMMY_HOLD,SPI_USR_DIN_HOLD,SPI_USR_DOUT_HOLD and SPI_USR_HOLD_POL. Can be configured in CONF state."]
71 #[inline(always)]
72 pub fn ext_hold_en(&self) -> EXT_HOLD_EN_R {
73 EXT_HOLD_EN_R::new(((self.bits >> 2) & 1) != 0)
74 }
75 #[doc = "Bit 3 - In the dummy phase the signal level of spi is output by the spi controller. Can be configured in CONF state."]
76 #[inline(always)]
77 pub fn dummy_out(&self) -> DUMMY_OUT_R {
78 DUMMY_OUT_R::new(((self.bits >> 3) & 1) != 0)
79 }
80 #[doc = "Bit 5 - Apply 2-bit mode during addr phase 1:enable 0: disable. Can be configured in CONF state."]
81 #[inline(always)]
82 pub fn faddr_dual(&self) -> FADDR_DUAL_R {
83 FADDR_DUAL_R::new(((self.bits >> 5) & 1) != 0)
84 }
85 #[doc = "Bit 6 - Apply 4-bit mode during addr phase 1:enable 0: disable. Can be configured in CONF state."]
86 #[inline(always)]
87 pub fn faddr_quad(&self) -> FADDR_QUAD_R {
88 FADDR_QUAD_R::new(((self.bits >> 6) & 1) != 0)
89 }
90 #[doc = "Bit 7 - Apply 8-bit mode during addr phase 1:enable 0: disable. Can be configured in CONF state."]
91 #[inline(always)]
92 pub fn faddr_oct(&self) -> FADDR_OCT_R {
93 FADDR_OCT_R::new(((self.bits >> 7) & 1) != 0)
94 }
95 #[doc = "Bit 8 - Apply 2-bit mode during command phase 1:enable 0: disable. Can be configured in CONF state."]
96 #[inline(always)]
97 pub fn fcmd_dual(&self) -> FCMD_DUAL_R {
98 FCMD_DUAL_R::new(((self.bits >> 8) & 1) != 0)
99 }
100 #[doc = "Bit 9 - Apply 4-bit mode during command phase 1:enable 0: disable. Can be configured in CONF state."]
101 #[inline(always)]
102 pub fn fcmd_quad(&self) -> FCMD_QUAD_R {
103 FCMD_QUAD_R::new(((self.bits >> 9) & 1) != 0)
104 }
105 #[doc = "Bit 10 - Apply 8-bit mode during command phase 1:enable 0: disable. Can be configured in CONF state."]
106 #[inline(always)]
107 pub fn fcmd_oct(&self) -> FCMD_OCT_R {
108 FCMD_OCT_R::new(((self.bits >> 10) & 1) != 0)
109 }
110 #[doc = "Bit 14 - In the read operations, read-data phase is in 2-bit mode. 1: enable 0: disable. Can be configured in CONF state."]
111 #[inline(always)]
112 pub fn fread_dual(&self) -> FREAD_DUAL_R {
113 FREAD_DUAL_R::new(((self.bits >> 14) & 1) != 0)
114 }
115 #[doc = "Bit 15 - In the read operations read-data phase is in 4-bit mode. 1: enable 0: disable. Can be configured in CONF state."]
116 #[inline(always)]
117 pub fn fread_quad(&self) -> FREAD_QUAD_R {
118 FREAD_QUAD_R::new(((self.bits >> 15) & 1) != 0)
119 }
120 #[doc = "Bit 16 - In the read operations read-data phase is in 8-bit mode. 1: enable 0: disable. Can be configured in CONF state."]
121 #[inline(always)]
122 pub fn fread_oct(&self) -> FREAD_OCT_R {
123 FREAD_OCT_R::new(((self.bits >> 16) & 1) != 0)
124 }
125 #[doc = "Bit 18 - The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state."]
126 #[inline(always)]
127 pub fn q_pol(&self) -> Q_POL_R {
128 Q_POL_R::new(((self.bits >> 18) & 1) != 0)
129 }
130 #[doc = "Bit 19 - The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state."]
131 #[inline(always)]
132 pub fn d_pol(&self) -> D_POL_R {
133 D_POL_R::new(((self.bits >> 19) & 1) != 0)
134 }
135 #[doc = "Bit 21 - Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state."]
136 #[inline(always)]
137 pub fn wp(&self) -> WP_R {
138 WP_R::new(((self.bits >> 21) & 1) != 0)
139 }
140 #[doc = "Bit 25 - In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state."]
141 #[inline(always)]
142 pub fn rd_bit_order(&self) -> RD_BIT_ORDER_R {
143 RD_BIT_ORDER_R::new(((self.bits >> 25) & 1) != 0)
144 }
145 #[doc = "Bit 26 - In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state."]
146 #[inline(always)]
147 pub fn wr_bit_order(&self) -> WR_BIT_ORDER_R {
148 WR_BIT_ORDER_R::new(((self.bits >> 26) & 1) != 0)
149 }
150}
151#[cfg(feature = "impl-register-debug")]
152impl core::fmt::Debug for R {
153 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
154 f.debug_struct("CTRL")
155 .field("ext_hold_en", &self.ext_hold_en())
156 .field("dummy_out", &self.dummy_out())
157 .field("faddr_dual", &self.faddr_dual())
158 .field("faddr_quad", &self.faddr_quad())
159 .field("faddr_oct", &self.faddr_oct())
160 .field("fcmd_dual", &self.fcmd_dual())
161 .field("fcmd_quad", &self.fcmd_quad())
162 .field("fcmd_oct", &self.fcmd_oct())
163 .field("fread_dual", &self.fread_dual())
164 .field("fread_quad", &self.fread_quad())
165 .field("fread_oct", &self.fread_oct())
166 .field("q_pol", &self.q_pol())
167 .field("d_pol", &self.d_pol())
168 .field("wp", &self.wp())
169 .field("rd_bit_order", &self.rd_bit_order())
170 .field("wr_bit_order", &self.wr_bit_order())
171 .finish()
172 }
173}
174impl W {
175 #[doc = "Bit 2 - Set the bit to hold spi. The bit is combined with SPI_USR_PREP_HOLD,SPI_USR_CMD_HOLD,SPI_USR_ADDR_HOLD,SPI_USR_DUMMY_HOLD,SPI_USR_DIN_HOLD,SPI_USR_DOUT_HOLD and SPI_USR_HOLD_POL. Can be configured in CONF state."]
176 #[inline(always)]
177 pub fn ext_hold_en(&mut self) -> EXT_HOLD_EN_W<CTRL_SPEC> {
178 EXT_HOLD_EN_W::new(self, 2)
179 }
180 #[doc = "Bit 3 - In the dummy phase the signal level of spi is output by the spi controller. Can be configured in CONF state."]
181 #[inline(always)]
182 pub fn dummy_out(&mut self) -> DUMMY_OUT_W<CTRL_SPEC> {
183 DUMMY_OUT_W::new(self, 3)
184 }
185 #[doc = "Bit 5 - Apply 2-bit mode during addr phase 1:enable 0: disable. Can be configured in CONF state."]
186 #[inline(always)]
187 pub fn faddr_dual(&mut self) -> FADDR_DUAL_W<CTRL_SPEC> {
188 FADDR_DUAL_W::new(self, 5)
189 }
190 #[doc = "Bit 6 - Apply 4-bit mode during addr phase 1:enable 0: disable. Can be configured in CONF state."]
191 #[inline(always)]
192 pub fn faddr_quad(&mut self) -> FADDR_QUAD_W<CTRL_SPEC> {
193 FADDR_QUAD_W::new(self, 6)
194 }
195 #[doc = "Bit 7 - Apply 8-bit mode during addr phase 1:enable 0: disable. Can be configured in CONF state."]
196 #[inline(always)]
197 pub fn faddr_oct(&mut self) -> FADDR_OCT_W<CTRL_SPEC> {
198 FADDR_OCT_W::new(self, 7)
199 }
200 #[doc = "Bit 8 - Apply 2-bit mode during command phase 1:enable 0: disable. Can be configured in CONF state."]
201 #[inline(always)]
202 pub fn fcmd_dual(&mut self) -> FCMD_DUAL_W<CTRL_SPEC> {
203 FCMD_DUAL_W::new(self, 8)
204 }
205 #[doc = "Bit 9 - Apply 4-bit mode during command phase 1:enable 0: disable. Can be configured in CONF state."]
206 #[inline(always)]
207 pub fn fcmd_quad(&mut self) -> FCMD_QUAD_W<CTRL_SPEC> {
208 FCMD_QUAD_W::new(self, 9)
209 }
210 #[doc = "Bit 10 - Apply 8-bit mode during command phase 1:enable 0: disable. Can be configured in CONF state."]
211 #[inline(always)]
212 pub fn fcmd_oct(&mut self) -> FCMD_OCT_W<CTRL_SPEC> {
213 FCMD_OCT_W::new(self, 10)
214 }
215 #[doc = "Bit 14 - In the read operations, read-data phase is in 2-bit mode. 1: enable 0: disable. Can be configured in CONF state."]
216 #[inline(always)]
217 pub fn fread_dual(&mut self) -> FREAD_DUAL_W<CTRL_SPEC> {
218 FREAD_DUAL_W::new(self, 14)
219 }
220 #[doc = "Bit 15 - In the read operations read-data phase is in 4-bit mode. 1: enable 0: disable. Can be configured in CONF state."]
221 #[inline(always)]
222 pub fn fread_quad(&mut self) -> FREAD_QUAD_W<CTRL_SPEC> {
223 FREAD_QUAD_W::new(self, 15)
224 }
225 #[doc = "Bit 16 - In the read operations read-data phase is in 8-bit mode. 1: enable 0: disable. Can be configured in CONF state."]
226 #[inline(always)]
227 pub fn fread_oct(&mut self) -> FREAD_OCT_W<CTRL_SPEC> {
228 FREAD_OCT_W::new(self, 16)
229 }
230 #[doc = "Bit 18 - The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state."]
231 #[inline(always)]
232 pub fn q_pol(&mut self) -> Q_POL_W<CTRL_SPEC> {
233 Q_POL_W::new(self, 18)
234 }
235 #[doc = "Bit 19 - The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state."]
236 #[inline(always)]
237 pub fn d_pol(&mut self) -> D_POL_W<CTRL_SPEC> {
238 D_POL_W::new(self, 19)
239 }
240 #[doc = "Bit 21 - Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state."]
241 #[inline(always)]
242 pub fn wp(&mut self) -> WP_W<CTRL_SPEC> {
243 WP_W::new(self, 21)
244 }
245 #[doc = "Bit 25 - In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state."]
246 #[inline(always)]
247 pub fn rd_bit_order(&mut self) -> RD_BIT_ORDER_W<CTRL_SPEC> {
248 RD_BIT_ORDER_W::new(self, 25)
249 }
250 #[doc = "Bit 26 - In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state."]
251 #[inline(always)]
252 pub fn wr_bit_order(&mut self) -> WR_BIT_ORDER_W<CTRL_SPEC> {
253 WR_BIT_ORDER_W::new(self, 26)
254 }
255}
256#[doc = "SPI control register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
257pub struct CTRL_SPEC;
258impl crate::RegisterSpec for CTRL_SPEC {
259 type Ux = u32;
260}
261#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"]
262impl crate::Readable for CTRL_SPEC {}
263#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"]
264impl crate::Writable for CTRL_SPEC {
265 type Safety = crate::Unsafe;
266}
267#[doc = "`reset()` method sets CTRL to value 0x002c_0000"]
268impl crate::Resettable for CTRL_SPEC {
269 const RESET_VALUE: u32 = 0x002c_0000;
270}