esp32s2/i2c0/
scl_high_period.rs

1#[doc = "Register `SCL_HIGH_PERIOD` reader"]
2pub type R = crate::R<SCL_HIGH_PERIOD_SPEC>;
3#[doc = "Register `SCL_HIGH_PERIOD` writer"]
4pub type W = crate::W<SCL_HIGH_PERIOD_SPEC>;
5#[doc = "Field `SCL_HIGH_PERIOD` reader - This register is used to configure for how long SCL remains high in master mode, in I2C module clock cycles."]
6pub type SCL_HIGH_PERIOD_R = crate::FieldReader<u16>;
7#[doc = "Field `SCL_HIGH_PERIOD` writer - This register is used to configure for how long SCL remains high in master mode, in I2C module clock cycles."]
8pub type SCL_HIGH_PERIOD_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>;
9#[doc = "Field `SCL_WAIT_HIGH_PERIOD` reader - This register is used to configure for the SCL_FSM's waiting period for SCL to go high in master mode, in I2C module clock cycles."]
10pub type SCL_WAIT_HIGH_PERIOD_R = crate::FieldReader<u16>;
11#[doc = "Field `SCL_WAIT_HIGH_PERIOD` writer - This register is used to configure for the SCL_FSM's waiting period for SCL to go high in master mode, in I2C module clock cycles."]
12pub type SCL_WAIT_HIGH_PERIOD_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>;
13impl R {
14    #[doc = "Bits 0:13 - This register is used to configure for how long SCL remains high in master mode, in I2C module clock cycles."]
15    #[inline(always)]
16    pub fn scl_high_period(&self) -> SCL_HIGH_PERIOD_R {
17        SCL_HIGH_PERIOD_R::new((self.bits & 0x3fff) as u16)
18    }
19    #[doc = "Bits 14:27 - This register is used to configure for the SCL_FSM's waiting period for SCL to go high in master mode, in I2C module clock cycles."]
20    #[inline(always)]
21    pub fn scl_wait_high_period(&self) -> SCL_WAIT_HIGH_PERIOD_R {
22        SCL_WAIT_HIGH_PERIOD_R::new(((self.bits >> 14) & 0x3fff) as u16)
23    }
24}
25#[cfg(feature = "impl-register-debug")]
26impl core::fmt::Debug for R {
27    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
28        f.debug_struct("SCL_HIGH_PERIOD")
29            .field("scl_high_period", &self.scl_high_period())
30            .field("scl_wait_high_period", &self.scl_wait_high_period())
31            .finish()
32    }
33}
34impl W {
35    #[doc = "Bits 0:13 - This register is used to configure for how long SCL remains high in master mode, in I2C module clock cycles."]
36    #[inline(always)]
37    pub fn scl_high_period(&mut self) -> SCL_HIGH_PERIOD_W<SCL_HIGH_PERIOD_SPEC> {
38        SCL_HIGH_PERIOD_W::new(self, 0)
39    }
40    #[doc = "Bits 14:27 - This register is used to configure for the SCL_FSM's waiting period for SCL to go high in master mode, in I2C module clock cycles."]
41    #[inline(always)]
42    pub fn scl_wait_high_period(&mut self) -> SCL_WAIT_HIGH_PERIOD_W<SCL_HIGH_PERIOD_SPEC> {
43        SCL_WAIT_HIGH_PERIOD_W::new(self, 14)
44    }
45}
46#[doc = "Configures the high level width of the SCL clock\n\nYou can [`read`](crate::Reg::read) this register and get [`scl_high_period::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scl_high_period::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
47pub struct SCL_HIGH_PERIOD_SPEC;
48impl crate::RegisterSpec for SCL_HIGH_PERIOD_SPEC {
49    type Ux = u32;
50}
51#[doc = "`read()` method returns [`scl_high_period::R`](R) reader structure"]
52impl crate::Readable for SCL_HIGH_PERIOD_SPEC {}
53#[doc = "`write(|w| ..)` method takes [`scl_high_period::W`](W) writer structure"]
54impl crate::Writable for SCL_HIGH_PERIOD_SPEC {
55    type Safety = crate::Unsafe;
56}
57#[doc = "`reset()` method sets SCL_HIGH_PERIOD to value 0"]
58impl crate::Resettable for SCL_HIGH_PERIOD_SPEC {}
esp32s2/i2c0/scl_high_period.rs

esp32s2/i2c0/
scl_high_period.rs
