esp32s2/timg0/
int_st.rs

1#[doc = "Register `INT_ST` reader"]
2pub type R = crate::R<INT_ST_SPEC>;
3#[doc = "Field `T(0-1)` reader - The masked interrupt status bit for the TIMG_T%s_INT interrupt."]
4pub type T_R = crate::BitReader;
5#[doc = "Field `WDT` reader - The masked interrupt status bit for the TIMG_WDT_INT interrupt."]
6pub type WDT_R = crate::BitReader;
7#[doc = "Field `LACT` reader - The masked interrupt status bit for the TIMG_LACT_INT interrupt."]
8pub type LACT_R = crate::BitReader;
9impl R {
10    #[doc = "The masked interrupt status bit for the TIMG_T(0-1)_INT interrupt."]
11    #[doc = ""]
12    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `T0` field.</div>"]
13    #[inline(always)]
14    pub fn t(&self, n: u8) -> T_R {
15        #[allow(clippy::no_effect)]
16        [(); 2][n as usize];
17        T_R::new(((self.bits >> n) & 1) != 0)
18    }
19    #[doc = "Iterator for array of:"]
20    #[doc = "The masked interrupt status bit for the TIMG_T(0-1)_INT interrupt."]
21    #[inline(always)]
22    pub fn t_iter(&self) -> impl Iterator<Item = T_R> + '_ {
23        (0..2).map(move |n| T_R::new(((self.bits >> n) & 1) != 0))
24    }
25    #[doc = "Bit 0 - The masked interrupt status bit for the TIMG_T0_INT interrupt."]
26    #[inline(always)]
27    pub fn t0(&self) -> T_R {
28        T_R::new((self.bits & 1) != 0)
29    }
30    #[doc = "Bit 1 - The masked interrupt status bit for the TIMG_T1_INT interrupt."]
31    #[inline(always)]
32    pub fn t1(&self) -> T_R {
33        T_R::new(((self.bits >> 1) & 1) != 0)
34    }
35    #[doc = "Bit 2 - The masked interrupt status bit for the TIMG_WDT_INT interrupt."]
36    #[inline(always)]
37    pub fn wdt(&self) -> WDT_R {
38        WDT_R::new(((self.bits >> 2) & 1) != 0)
39    }
40    #[doc = "Bit 3 - The masked interrupt status bit for the TIMG_LACT_INT interrupt."]
41    #[inline(always)]
42    pub fn lact(&self) -> LACT_R {
43        LACT_R::new(((self.bits >> 3) & 1) != 0)
44    }
45}
46#[cfg(feature = "impl-register-debug")]
47impl core::fmt::Debug for R {
48    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
49        f.debug_struct("INT_ST")
50            .field("t0", &self.t0())
51            .field("t1", &self.t1())
52            .field("wdt", &self.wdt())
53            .field("lact", &self.lact())
54            .finish()
55    }
56}
57#[doc = "Masked interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
58pub struct INT_ST_SPEC;
59impl crate::RegisterSpec for INT_ST_SPEC {
60    type Ux = u32;
61}
62#[doc = "`read()` method returns [`int_st::R`](R) reader structure"]
63impl crate::Readable for INT_ST_SPEC {}
64#[doc = "`reset()` method sets INT_ST to value 0"]
65impl crate::Resettable for INT_ST_SPEC {}
esp32s2/timg0/int_st.rs

esp32s2/timg0/
int_st.rs
