1#[doc = "Register `LCD_D_NUM` reader"]
2pub type R = crate::R<LCD_D_NUM_SPEC>;
3#[doc = "Register `LCD_D_NUM` writer"]
4pub type W = crate::W<LCD_D_NUM_SPEC>;
5#[doc = "Field `D_DQS_NUM` reader - the output spi_dqs is delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
6pub type D_DQS_NUM_R = crate::FieldReader;
7#[doc = "Field `D_DQS_NUM` writer - the output spi_dqs is delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
8pub type D_DQS_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
9#[doc = "Field `D_CD_NUM` reader - the output spi_cd is delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
10pub type D_CD_NUM_R = crate::FieldReader;
11#[doc = "Field `D_CD_NUM` writer - the output spi_cd is delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
12pub type D_CD_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
13#[doc = "Field `D_DE_NUM` reader - the output spi_de is delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
14pub type D_DE_NUM_R = crate::FieldReader;
15#[doc = "Field `D_DE_NUM` writer - the output spi_de is delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
16pub type D_DE_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
17#[doc = "Field `D_HSYNC_NUM` reader - the output spi_hsync is delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
18pub type D_HSYNC_NUM_R = crate::FieldReader;
19#[doc = "Field `D_HSYNC_NUM` writer - the output spi_hsync is delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
20pub type D_HSYNC_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
21#[doc = "Field `D_VSYNC_NUM` reader - the output spi_vsync is delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
22pub type D_VSYNC_NUM_R = crate::FieldReader;
23#[doc = "Field `D_VSYNC_NUM` writer - the output spi_vsync is delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
24pub type D_VSYNC_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
25impl R {
26 #[doc = "Bits 0:1 - the output spi_dqs is delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
27 #[inline(always)]
28 pub fn d_dqs_num(&self) -> D_DQS_NUM_R {
29 D_DQS_NUM_R::new((self.bits & 3) as u8)
30 }
31 #[doc = "Bits 2:3 - the output spi_cd is delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
32 #[inline(always)]
33 pub fn d_cd_num(&self) -> D_CD_NUM_R {
34 D_CD_NUM_R::new(((self.bits >> 2) & 3) as u8)
35 }
36 #[doc = "Bits 4:5 - the output spi_de is delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
37 #[inline(always)]
38 pub fn d_de_num(&self) -> D_DE_NUM_R {
39 D_DE_NUM_R::new(((self.bits >> 4) & 3) as u8)
40 }
41 #[doc = "Bits 6:7 - the output spi_hsync is delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
42 #[inline(always)]
43 pub fn d_hsync_num(&self) -> D_HSYNC_NUM_R {
44 D_HSYNC_NUM_R::new(((self.bits >> 6) & 3) as u8)
45 }
46 #[doc = "Bits 8:9 - the output spi_vsync is delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
47 #[inline(always)]
48 pub fn d_vsync_num(&self) -> D_VSYNC_NUM_R {
49 D_VSYNC_NUM_R::new(((self.bits >> 8) & 3) as u8)
50 }
51}
52#[cfg(feature = "impl-register-debug")]
53impl core::fmt::Debug for R {
54 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
55 f.debug_struct("LCD_D_NUM")
56 .field("d_dqs_num", &self.d_dqs_num())
57 .field("d_cd_num", &self.d_cd_num())
58 .field("d_de_num", &self.d_de_num())
59 .field("d_hsync_num", &self.d_hsync_num())
60 .field("d_vsync_num", &self.d_vsync_num())
61 .finish()
62 }
63}
64impl W {
65 #[doc = "Bits 0:1 - the output spi_dqs is delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
66 #[inline(always)]
67 pub fn d_dqs_num(&mut self) -> D_DQS_NUM_W<LCD_D_NUM_SPEC> {
68 D_DQS_NUM_W::new(self, 0)
69 }
70 #[doc = "Bits 2:3 - the output spi_cd is delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
71 #[inline(always)]
72 pub fn d_cd_num(&mut self) -> D_CD_NUM_W<LCD_D_NUM_SPEC> {
73 D_CD_NUM_W::new(self, 2)
74 }
75 #[doc = "Bits 4:5 - the output spi_de is delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
76 #[inline(always)]
77 pub fn d_de_num(&mut self) -> D_DE_NUM_W<LCD_D_NUM_SPEC> {
78 D_DE_NUM_W::new(self, 4)
79 }
80 #[doc = "Bits 6:7 - the output spi_hsync is delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
81 #[inline(always)]
82 pub fn d_hsync_num(&mut self) -> D_HSYNC_NUM_W<LCD_D_NUM_SPEC> {
83 D_HSYNC_NUM_W::new(self, 6)
84 }
85 #[doc = "Bits 8:9 - the output spi_vsync is delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
86 #[inline(always)]
87 pub fn d_vsync_num(&mut self) -> D_VSYNC_NUM_W<LCD_D_NUM_SPEC> {
88 D_VSYNC_NUM_W::new(self, 8)
89 }
90}
91#[doc = "LCD delay mode\n\nYou can [`read`](crate::Reg::read) this register and get [`lcd_d_num::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcd_d_num::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
92pub struct LCD_D_NUM_SPEC;
93impl crate::RegisterSpec for LCD_D_NUM_SPEC {
94 type Ux = u32;
95}
96#[doc = "`read()` method returns [`lcd_d_num::R`](R) reader structure"]
97impl crate::Readable for LCD_D_NUM_SPEC {}
98#[doc = "`write(|w| ..)` method takes [`lcd_d_num::W`](W) writer structure"]
99impl crate::Writable for LCD_D_NUM_SPEC {
100 type Safety = crate::Unsafe;
101}
102#[doc = "`reset()` method sets LCD_D_NUM to value 0"]
103impl crate::Resettable for LCD_D_NUM_SPEC {}