1#[doc = "Register `LCD_D_MODE` reader"]
2pub type R = crate::R<LCD_D_MODE_SPEC>;
3#[doc = "Register `LCD_D_MODE` writer"]
4pub type W = crate::W<LCD_D_MODE_SPEC>;
5#[doc = "Field `D_DQS_MODE` reader - the output spi_dqs is delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state."]
6pub type D_DQS_MODE_R = crate::FieldReader;
7#[doc = "Field `D_DQS_MODE` writer - the output spi_dqs is delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state."]
8pub type D_DQS_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
9#[doc = "Field `D_CD_MODE` reader - the output spi_cd is delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state."]
10pub type D_CD_MODE_R = crate::FieldReader;
11#[doc = "Field `D_CD_MODE` writer - the output spi_cd is delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state."]
12pub type D_CD_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
13#[doc = "Field `D_DE_MODE` reader - the output spi_de is delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state."]
14pub type D_DE_MODE_R = crate::FieldReader;
15#[doc = "Field `D_DE_MODE` writer - the output spi_de is delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state."]
16pub type D_DE_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
17#[doc = "Field `D_HSYNC_MODE` reader - the output spi_hsync is delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state."]
18pub type D_HSYNC_MODE_R = crate::FieldReader;
19#[doc = "Field `D_HSYNC_MODE` writer - the output spi_hsync is delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state."]
20pub type D_HSYNC_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
21#[doc = "Field `D_VSYNC_MODE` reader - the output spi_vsync is delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state."]
22pub type D_VSYNC_MODE_R = crate::FieldReader;
23#[doc = "Field `D_VSYNC_MODE` writer - the output spi_vsync is delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state."]
24pub type D_VSYNC_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
25#[doc = "Field `DE_IDLE_POL` reader - It is the idle value of spi_de."]
26pub type DE_IDLE_POL_R = crate::BitReader;
27#[doc = "Field `DE_IDLE_POL` writer - It is the idle value of spi_de."]
28pub type DE_IDLE_POL_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `HS_BLANK_EN` reader - 1: The pulse of spi_hsync is out in vertical blanking lines in seg-trans or one trans. 0: spi_hsync pulse is valid only in active region lines in seg-trans."]
30pub type HS_BLANK_EN_R = crate::BitReader;
31#[doc = "Field `HS_BLANK_EN` writer - 1: The pulse of spi_hsync is out in vertical blanking lines in seg-trans or one trans. 0: spi_hsync pulse is valid only in active region lines in seg-trans."]
32pub type HS_BLANK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
33impl R {
34 #[doc = "Bits 0:2 - the output spi_dqs is delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state."]
35 #[inline(always)]
36 pub fn d_dqs_mode(&self) -> D_DQS_MODE_R {
37 D_DQS_MODE_R::new((self.bits & 7) as u8)
38 }
39 #[doc = "Bits 3:5 - the output spi_cd is delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state."]
40 #[inline(always)]
41 pub fn d_cd_mode(&self) -> D_CD_MODE_R {
42 D_CD_MODE_R::new(((self.bits >> 3) & 7) as u8)
43 }
44 #[doc = "Bits 6:8 - the output spi_de is delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state."]
45 #[inline(always)]
46 pub fn d_de_mode(&self) -> D_DE_MODE_R {
47 D_DE_MODE_R::new(((self.bits >> 6) & 7) as u8)
48 }
49 #[doc = "Bits 9:11 - the output spi_hsync is delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state."]
50 #[inline(always)]
51 pub fn d_hsync_mode(&self) -> D_HSYNC_MODE_R {
52 D_HSYNC_MODE_R::new(((self.bits >> 9) & 7) as u8)
53 }
54 #[doc = "Bits 12:14 - the output spi_vsync is delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state."]
55 #[inline(always)]
56 pub fn d_vsync_mode(&self) -> D_VSYNC_MODE_R {
57 D_VSYNC_MODE_R::new(((self.bits >> 12) & 7) as u8)
58 }
59 #[doc = "Bit 15 - It is the idle value of spi_de."]
60 #[inline(always)]
61 pub fn de_idle_pol(&self) -> DE_IDLE_POL_R {
62 DE_IDLE_POL_R::new(((self.bits >> 15) & 1) != 0)
63 }
64 #[doc = "Bit 16 - 1: The pulse of spi_hsync is out in vertical blanking lines in seg-trans or one trans. 0: spi_hsync pulse is valid only in active region lines in seg-trans."]
65 #[inline(always)]
66 pub fn hs_blank_en(&self) -> HS_BLANK_EN_R {
67 HS_BLANK_EN_R::new(((self.bits >> 16) & 1) != 0)
68 }
69}
70#[cfg(feature = "impl-register-debug")]
71impl core::fmt::Debug for R {
72 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
73 f.debug_struct("LCD_D_MODE")
74 .field("d_dqs_mode", &self.d_dqs_mode())
75 .field("d_cd_mode", &self.d_cd_mode())
76 .field("d_de_mode", &self.d_de_mode())
77 .field("d_hsync_mode", &self.d_hsync_mode())
78 .field("d_vsync_mode", &self.d_vsync_mode())
79 .field("de_idle_pol", &self.de_idle_pol())
80 .field("hs_blank_en", &self.hs_blank_en())
81 .finish()
82 }
83}
84impl W {
85 #[doc = "Bits 0:2 - the output spi_dqs is delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state."]
86 #[inline(always)]
87 pub fn d_dqs_mode(&mut self) -> D_DQS_MODE_W<LCD_D_MODE_SPEC> {
88 D_DQS_MODE_W::new(self, 0)
89 }
90 #[doc = "Bits 3:5 - the output spi_cd is delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state."]
91 #[inline(always)]
92 pub fn d_cd_mode(&mut self) -> D_CD_MODE_W<LCD_D_MODE_SPEC> {
93 D_CD_MODE_W::new(self, 3)
94 }
95 #[doc = "Bits 6:8 - the output spi_de is delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state."]
96 #[inline(always)]
97 pub fn d_de_mode(&mut self) -> D_DE_MODE_W<LCD_D_MODE_SPEC> {
98 D_DE_MODE_W::new(self, 6)
99 }
100 #[doc = "Bits 9:11 - the output spi_hsync is delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state."]
101 #[inline(always)]
102 pub fn d_hsync_mode(&mut self) -> D_HSYNC_MODE_W<LCD_D_MODE_SPEC> {
103 D_HSYNC_MODE_W::new(self, 9)
104 }
105 #[doc = "Bits 12:14 - the output spi_vsync is delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state."]
106 #[inline(always)]
107 pub fn d_vsync_mode(&mut self) -> D_VSYNC_MODE_W<LCD_D_MODE_SPEC> {
108 D_VSYNC_MODE_W::new(self, 12)
109 }
110 #[doc = "Bit 15 - It is the idle value of spi_de."]
111 #[inline(always)]
112 pub fn de_idle_pol(&mut self) -> DE_IDLE_POL_W<LCD_D_MODE_SPEC> {
113 DE_IDLE_POL_W::new(self, 15)
114 }
115 #[doc = "Bit 16 - 1: The pulse of spi_hsync is out in vertical blanking lines in seg-trans or one trans. 0: spi_hsync pulse is valid only in active region lines in seg-trans."]
116 #[inline(always)]
117 pub fn hs_blank_en(&mut self) -> HS_BLANK_EN_W<LCD_D_MODE_SPEC> {
118 HS_BLANK_EN_W::new(self, 16)
119 }
120}
121#[doc = "LCD delay number\n\nYou can [`read`](crate::Reg::read) this register and get [`lcd_d_mode::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcd_d_mode::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
122pub struct LCD_D_MODE_SPEC;
123impl crate::RegisterSpec for LCD_D_MODE_SPEC {
124 type Ux = u32;
125}
126#[doc = "`read()` method returns [`lcd_d_mode::R`](R) reader structure"]
127impl crate::Readable for LCD_D_MODE_SPEC {}
128#[doc = "`write(|w| ..)` method takes [`lcd_d_mode::W`](W) writer structure"]
129impl crate::Writable for LCD_D_MODE_SPEC {
130 type Safety = crate::Unsafe;
131}
132#[doc = "`reset()` method sets LCD_D_MODE to value 0"]
133impl crate::Resettable for LCD_D_MODE_SPEC {}