esp32s2/spi2/
lcd_ctrl2.rs

1#[doc = "Register `LCD_CTRL2` reader"]
2pub type R = crate::R<LCD_CTRL2_SPEC>;
3#[doc = "Register `LCD_CTRL2` writer"]
4pub type W = crate::W<LCD_CTRL2_SPEC>;
5#[doc = "Field `LCD_VSYNC_WIDTH` reader - It is the position of spi_vsync active pulse in a line. Can be configured in CONF state."]
6pub type LCD_VSYNC_WIDTH_R = crate::FieldReader;
7#[doc = "Field `LCD_VSYNC_WIDTH` writer - It is the position of spi_vsync active pulse in a line. Can be configured in CONF state."]
8pub type LCD_VSYNC_WIDTH_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
9#[doc = "Field `VSYNC_IDLE_POL` reader - It is the idle value of spi_vsync. Can be configured in CONF state."]
10pub type VSYNC_IDLE_POL_R = crate::BitReader;
11#[doc = "Field `VSYNC_IDLE_POL` writer - It is the idle value of spi_vsync. Can be configured in CONF state."]
12pub type VSYNC_IDLE_POL_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `LCD_HSYNC_WIDTH` reader - It is the position of spi_hsync active pulse in a line. Can be configured in CONF state."]
14pub type LCD_HSYNC_WIDTH_R = crate::FieldReader;
15#[doc = "Field `LCD_HSYNC_WIDTH` writer - It is the position of spi_hsync active pulse in a line. Can be configured in CONF state."]
16pub type LCD_HSYNC_WIDTH_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
17#[doc = "Field `HSYNC_IDLE_POL` reader - It is the idle value of spi_hsync. Can be configured in CONF state."]
18pub type HSYNC_IDLE_POL_R = crate::BitReader;
19#[doc = "Field `HSYNC_IDLE_POL` writer - It is the idle value of spi_hsync. Can be configured in CONF state."]
20pub type HSYNC_IDLE_POL_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `LCD_HSYNC_POSITION` reader - It is the position of spi_hsync active pulse in a line. Can be configured in CONF state."]
22pub type LCD_HSYNC_POSITION_R = crate::FieldReader;
23#[doc = "Field `LCD_HSYNC_POSITION` writer - It is the position of spi_hsync active pulse in a line. Can be configured in CONF state."]
24pub type LCD_HSYNC_POSITION_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
25impl R {
26    #[doc = "Bits 0:6 - It is the position of spi_vsync active pulse in a line. Can be configured in CONF state."]
27    #[inline(always)]
28    pub fn lcd_vsync_width(&self) -> LCD_VSYNC_WIDTH_R {
29        LCD_VSYNC_WIDTH_R::new((self.bits & 0x7f) as u8)
30    }
31    #[doc = "Bit 7 - It is the idle value of spi_vsync. Can be configured in CONF state."]
32    #[inline(always)]
33    pub fn vsync_idle_pol(&self) -> VSYNC_IDLE_POL_R {
34        VSYNC_IDLE_POL_R::new(((self.bits >> 7) & 1) != 0)
35    }
36    #[doc = "Bits 16:22 - It is the position of spi_hsync active pulse in a line. Can be configured in CONF state."]
37    #[inline(always)]
38    pub fn lcd_hsync_width(&self) -> LCD_HSYNC_WIDTH_R {
39        LCD_HSYNC_WIDTH_R::new(((self.bits >> 16) & 0x7f) as u8)
40    }
41    #[doc = "Bit 23 - It is the idle value of spi_hsync. Can be configured in CONF state."]
42    #[inline(always)]
43    pub fn hsync_idle_pol(&self) -> HSYNC_IDLE_POL_R {
44        HSYNC_IDLE_POL_R::new(((self.bits >> 23) & 1) != 0)
45    }
46    #[doc = "Bits 24:31 - It is the position of spi_hsync active pulse in a line. Can be configured in CONF state."]
47    #[inline(always)]
48    pub fn lcd_hsync_position(&self) -> LCD_HSYNC_POSITION_R {
49        LCD_HSYNC_POSITION_R::new(((self.bits >> 24) & 0xff) as u8)
50    }
51}
52#[cfg(feature = "impl-register-debug")]
53impl core::fmt::Debug for R {
54    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
55        f.debug_struct("LCD_CTRL2")
56            .field("lcd_vsync_width", &self.lcd_vsync_width())
57            .field("vsync_idle_pol", &self.vsync_idle_pol())
58            .field("lcd_hsync_width", &self.lcd_hsync_width())
59            .field("hsync_idle_pol", &self.hsync_idle_pol())
60            .field("lcd_hsync_position", &self.lcd_hsync_position())
61            .finish()
62    }
63}
64impl W {
65    #[doc = "Bits 0:6 - It is the position of spi_vsync active pulse in a line. Can be configured in CONF state."]
66    #[inline(always)]
67    pub fn lcd_vsync_width(&mut self) -> LCD_VSYNC_WIDTH_W<LCD_CTRL2_SPEC> {
68        LCD_VSYNC_WIDTH_W::new(self, 0)
69    }
70    #[doc = "Bit 7 - It is the idle value of spi_vsync. Can be configured in CONF state."]
71    #[inline(always)]
72    pub fn vsync_idle_pol(&mut self) -> VSYNC_IDLE_POL_W<LCD_CTRL2_SPEC> {
73        VSYNC_IDLE_POL_W::new(self, 7)
74    }
75    #[doc = "Bits 16:22 - It is the position of spi_hsync active pulse in a line. Can be configured in CONF state."]
76    #[inline(always)]
77    pub fn lcd_hsync_width(&mut self) -> LCD_HSYNC_WIDTH_W<LCD_CTRL2_SPEC> {
78        LCD_HSYNC_WIDTH_W::new(self, 16)
79    }
80    #[doc = "Bit 23 - It is the idle value of spi_hsync. Can be configured in CONF state."]
81    #[inline(always)]
82    pub fn hsync_idle_pol(&mut self) -> HSYNC_IDLE_POL_W<LCD_CTRL2_SPEC> {
83        HSYNC_IDLE_POL_W::new(self, 23)
84    }
85    #[doc = "Bits 24:31 - It is the position of spi_hsync active pulse in a line. Can be configured in CONF state."]
86    #[inline(always)]
87    pub fn lcd_hsync_position(&mut self) -> LCD_HSYNC_POSITION_W<LCD_CTRL2_SPEC> {
88        LCD_HSYNC_POSITION_W::new(self, 24)
89    }
90}
91#[doc = "LCD frame control2 register\n\nYou can [`read`](crate::Reg::read) this register and get [`lcd_ctrl2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcd_ctrl2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
92pub struct LCD_CTRL2_SPEC;
93impl crate::RegisterSpec for LCD_CTRL2_SPEC {
94    type Ux = u32;
95}
96#[doc = "`read()` method returns [`lcd_ctrl2::R`](R) reader structure"]
97impl crate::Readable for LCD_CTRL2_SPEC {}
98#[doc = "`write(|w| ..)` method takes [`lcd_ctrl2::W`](W) writer structure"]
99impl crate::Writable for LCD_CTRL2_SPEC {
100    type Safety = crate::Unsafe;
101}
102#[doc = "`reset()` method sets LCD_CTRL2 to value 0x0001_0001"]
103impl crate::Resettable for LCD_CTRL2_SPEC {
104    const RESET_VALUE: u32 = 0x0001_0001;
105}
esp32s2/spi2/lcd_ctrl2.rs

esp32s2/spi2/
lcd_ctrl2.rs
