esp32s2/rtc_cntl/
clk_conf.rs1#[doc = "Register `CLK_CONF` reader"]
2pub type R = crate::R<CLK_CONF_SPEC>;
3#[doc = "Register `CLK_CONF` writer"]
4pub type W = crate::W<CLK_CONF_SPEC>;
5#[doc = "Field `CK8M_DIV_SEL_VLD` reader - Synchronizes the reg_ck8m_div_sel. Not that you have to invalidate the bus before switching clock, and validate the new clock."]
6pub type CK8M_DIV_SEL_VLD_R = crate::BitReader;
7#[doc = "Field `CK8M_DIV_SEL_VLD` writer - Synchronizes the reg_ck8m_div_sel. Not that you have to invalidate the bus before switching clock, and validate the new clock."]
8pub type CK8M_DIV_SEL_VLD_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `CK8M_DIV` reader - Set the CK8M_D256_OUT divider. 00: divided by 128 01: divided by 256 10: divided by 512 11: divided by 1024."]
10pub type CK8M_DIV_R = crate::FieldReader;
11#[doc = "Field `CK8M_DIV` writer - Set the CK8M_D256_OUT divider. 00: divided by 128 01: divided by 256 10: divided by 512 11: divided by 1024."]
12pub type CK8M_DIV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
13#[doc = "Field `ENB_CK8M` reader - Set this bit to disable CK8M and CK8M_D256_OUT."]
14pub type ENB_CK8M_R = crate::BitReader;
15#[doc = "Field `ENB_CK8M` writer - Set this bit to disable CK8M and CK8M_D256_OUT."]
16pub type ENB_CK8M_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `ENB_CK8M_DIV` reader - Selects the CK8M_D256_OUT. 1: CK8M 0: CK8M divided by 256."]
18pub type ENB_CK8M_DIV_R = crate::BitReader;
19#[doc = "Field `ENB_CK8M_DIV` writer - Selects the CK8M_D256_OUT. 1: CK8M 0: CK8M divided by 256."]
20pub type ENB_CK8M_DIV_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `DIG_XTAL32K_EN` reader - Set this bit to enable CK_XTAL_32K clock for the digital core."]
22pub type DIG_XTAL32K_EN_R = crate::BitReader;
23#[doc = "Field `DIG_XTAL32K_EN` writer - Set this bit to enable CK_XTAL_32K clock for the digital core."]
24pub type DIG_XTAL32K_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `DIG_CLK8M_D256_EN` reader - Set this bit to enable CK8M_D256_OUT clock for the digital core."]
26pub type DIG_CLK8M_D256_EN_R = crate::BitReader;
27#[doc = "Field `DIG_CLK8M_D256_EN` writer - Set this bit to enable CK8M_D256_OUT clock for the digital core."]
28pub type DIG_CLK8M_D256_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `DIG_CLK8M_EN` reader - Set this bit to enable 8 MHz clock for the digital core."]
30pub type DIG_CLK8M_EN_R = crate::BitReader;
31#[doc = "Field `DIG_CLK8M_EN` writer - Set this bit to enable 8 MHz clock for the digital core."]
32pub type DIG_CLK8M_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `CK8M_DIV_SEL` reader - Stores the 8 MHz divider, which is reg_ck8m_div_sel + 1"]
34pub type CK8M_DIV_SEL_R = crate::FieldReader;
35#[doc = "Field `CK8M_DIV_SEL` writer - Stores the 8 MHz divider, which is reg_ck8m_div_sel + 1"]
36pub type CK8M_DIV_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
37#[doc = "Field `XTAL_FORCE_NOGATING` reader - Set this bit to force no gating to crystal during sleep"]
38pub type XTAL_FORCE_NOGATING_R = crate::BitReader;
39#[doc = "Field `XTAL_FORCE_NOGATING` writer - Set this bit to force no gating to crystal during sleep"]
40pub type XTAL_FORCE_NOGATING_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `CK8M_FORCE_NOGATING` reader - Set this bit to disable force gating to 8 MHz crystal during sleep."]
42pub type CK8M_FORCE_NOGATING_R = crate::BitReader;
43#[doc = "Field `CK8M_FORCE_NOGATING` writer - Set this bit to disable force gating to 8 MHz crystal during sleep."]
44pub type CK8M_FORCE_NOGATING_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `CK8M_DFREQ` reader - CK8M_DFREQ"]
46pub type CK8M_DFREQ_R = crate::FieldReader;
47#[doc = "Field `CK8M_DFREQ` writer - CK8M_DFREQ"]
48pub type CK8M_DFREQ_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
49#[doc = "Field `CK8M_FORCE_PD` reader - Set this bit to FPD the 8 MHz clock."]
50pub type CK8M_FORCE_PD_R = crate::BitReader;
51#[doc = "Field `CK8M_FORCE_PD` writer - Set this bit to FPD the 8 MHz clock."]
52pub type CK8M_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `CK8M_FORCE_PU` reader - Set this bit to FPU the 8 MHz clock."]
54pub type CK8M_FORCE_PU_R = crate::BitReader;
55#[doc = "Field `CK8M_FORCE_PU` writer - Set this bit to FPU the 8 MHz clock."]
56pub type CK8M_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `FAST_CLK_RTC_SEL` reader - Set this bit to select the RTC fast clock. 0: XTAL div 4, 1: CK8M."]
58pub type FAST_CLK_RTC_SEL_R = crate::BitReader;
59#[doc = "Field `FAST_CLK_RTC_SEL` writer - Set this bit to select the RTC fast clock. 0: XTAL div 4, 1: CK8M."]
60pub type FAST_CLK_RTC_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `ANA_CLK_RTC_SEL` reader - Set this bit to select the RTC slow clock. 0: 90K rtc_clk 1: 32k XTAL 2: 8md256."]
62pub type ANA_CLK_RTC_SEL_R = crate::FieldReader;
63#[doc = "Field `ANA_CLK_RTC_SEL` writer - Set this bit to select the RTC slow clock. 0: 90K rtc_clk 1: 32k XTAL 2: 8md256."]
64pub type ANA_CLK_RTC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
65impl R {
66 #[doc = "Bit 3 - Synchronizes the reg_ck8m_div_sel. Not that you have to invalidate the bus before switching clock, and validate the new clock."]
67 #[inline(always)]
68 pub fn ck8m_div_sel_vld(&self) -> CK8M_DIV_SEL_VLD_R {
69 CK8M_DIV_SEL_VLD_R::new(((self.bits >> 3) & 1) != 0)
70 }
71 #[doc = "Bits 4:5 - Set the CK8M_D256_OUT divider. 00: divided by 128 01: divided by 256 10: divided by 512 11: divided by 1024."]
72 #[inline(always)]
73 pub fn ck8m_div(&self) -> CK8M_DIV_R {
74 CK8M_DIV_R::new(((self.bits >> 4) & 3) as u8)
75 }
76 #[doc = "Bit 6 - Set this bit to disable CK8M and CK8M_D256_OUT."]
77 #[inline(always)]
78 pub fn enb_ck8m(&self) -> ENB_CK8M_R {
79 ENB_CK8M_R::new(((self.bits >> 6) & 1) != 0)
80 }
81 #[doc = "Bit 7 - Selects the CK8M_D256_OUT. 1: CK8M 0: CK8M divided by 256."]
82 #[inline(always)]
83 pub fn enb_ck8m_div(&self) -> ENB_CK8M_DIV_R {
84 ENB_CK8M_DIV_R::new(((self.bits >> 7) & 1) != 0)
85 }
86 #[doc = "Bit 8 - Set this bit to enable CK_XTAL_32K clock for the digital core."]
87 #[inline(always)]
88 pub fn dig_xtal32k_en(&self) -> DIG_XTAL32K_EN_R {
89 DIG_XTAL32K_EN_R::new(((self.bits >> 8) & 1) != 0)
90 }
91 #[doc = "Bit 9 - Set this bit to enable CK8M_D256_OUT clock for the digital core."]
92 #[inline(always)]
93 pub fn dig_clk8m_d256_en(&self) -> DIG_CLK8M_D256_EN_R {
94 DIG_CLK8M_D256_EN_R::new(((self.bits >> 9) & 1) != 0)
95 }
96 #[doc = "Bit 10 - Set this bit to enable 8 MHz clock for the digital core."]
97 #[inline(always)]
98 pub fn dig_clk8m_en(&self) -> DIG_CLK8M_EN_R {
99 DIG_CLK8M_EN_R::new(((self.bits >> 10) & 1) != 0)
100 }
101 #[doc = "Bits 12:14 - Stores the 8 MHz divider, which is reg_ck8m_div_sel + 1"]
102 #[inline(always)]
103 pub fn ck8m_div_sel(&self) -> CK8M_DIV_SEL_R {
104 CK8M_DIV_SEL_R::new(((self.bits >> 12) & 7) as u8)
105 }
106 #[doc = "Bit 15 - Set this bit to force no gating to crystal during sleep"]
107 #[inline(always)]
108 pub fn xtal_force_nogating(&self) -> XTAL_FORCE_NOGATING_R {
109 XTAL_FORCE_NOGATING_R::new(((self.bits >> 15) & 1) != 0)
110 }
111 #[doc = "Bit 16 - Set this bit to disable force gating to 8 MHz crystal during sleep."]
112 #[inline(always)]
113 pub fn ck8m_force_nogating(&self) -> CK8M_FORCE_NOGATING_R {
114 CK8M_FORCE_NOGATING_R::new(((self.bits >> 16) & 1) != 0)
115 }
116 #[doc = "Bits 17:24 - CK8M_DFREQ"]
117 #[inline(always)]
118 pub fn ck8m_dfreq(&self) -> CK8M_DFREQ_R {
119 CK8M_DFREQ_R::new(((self.bits >> 17) & 0xff) as u8)
120 }
121 #[doc = "Bit 25 - Set this bit to FPD the 8 MHz clock."]
122 #[inline(always)]
123 pub fn ck8m_force_pd(&self) -> CK8M_FORCE_PD_R {
124 CK8M_FORCE_PD_R::new(((self.bits >> 25) & 1) != 0)
125 }
126 #[doc = "Bit 26 - Set this bit to FPU the 8 MHz clock."]
127 #[inline(always)]
128 pub fn ck8m_force_pu(&self) -> CK8M_FORCE_PU_R {
129 CK8M_FORCE_PU_R::new(((self.bits >> 26) & 1) != 0)
130 }
131 #[doc = "Bit 29 - Set this bit to select the RTC fast clock. 0: XTAL div 4, 1: CK8M."]
132 #[inline(always)]
133 pub fn fast_clk_rtc_sel(&self) -> FAST_CLK_RTC_SEL_R {
134 FAST_CLK_RTC_SEL_R::new(((self.bits >> 29) & 1) != 0)
135 }
136 #[doc = "Bits 30:31 - Set this bit to select the RTC slow clock. 0: 90K rtc_clk 1: 32k XTAL 2: 8md256."]
137 #[inline(always)]
138 pub fn ana_clk_rtc_sel(&self) -> ANA_CLK_RTC_SEL_R {
139 ANA_CLK_RTC_SEL_R::new(((self.bits >> 30) & 3) as u8)
140 }
141}
142#[cfg(feature = "impl-register-debug")]
143impl core::fmt::Debug for R {
144 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
145 f.debug_struct("CLK_CONF")
146 .field("ck8m_div_sel_vld", &self.ck8m_div_sel_vld())
147 .field("ck8m_div", &self.ck8m_div())
148 .field("enb_ck8m", &self.enb_ck8m())
149 .field("enb_ck8m_div", &self.enb_ck8m_div())
150 .field("dig_xtal32k_en", &self.dig_xtal32k_en())
151 .field("dig_clk8m_d256_en", &self.dig_clk8m_d256_en())
152 .field("dig_clk8m_en", &self.dig_clk8m_en())
153 .field("ck8m_div_sel", &self.ck8m_div_sel())
154 .field("xtal_force_nogating", &self.xtal_force_nogating())
155 .field("ck8m_force_nogating", &self.ck8m_force_nogating())
156 .field("ck8m_dfreq", &self.ck8m_dfreq())
157 .field("ck8m_force_pd", &self.ck8m_force_pd())
158 .field("ck8m_force_pu", &self.ck8m_force_pu())
159 .field("fast_clk_rtc_sel", &self.fast_clk_rtc_sel())
160 .field("ana_clk_rtc_sel", &self.ana_clk_rtc_sel())
161 .finish()
162 }
163}
164impl W {
165 #[doc = "Bit 3 - Synchronizes the reg_ck8m_div_sel. Not that you have to invalidate the bus before switching clock, and validate the new clock."]
166 #[inline(always)]
167 pub fn ck8m_div_sel_vld(&mut self) -> CK8M_DIV_SEL_VLD_W<CLK_CONF_SPEC> {
168 CK8M_DIV_SEL_VLD_W::new(self, 3)
169 }
170 #[doc = "Bits 4:5 - Set the CK8M_D256_OUT divider. 00: divided by 128 01: divided by 256 10: divided by 512 11: divided by 1024."]
171 #[inline(always)]
172 pub fn ck8m_div(&mut self) -> CK8M_DIV_W<CLK_CONF_SPEC> {
173 CK8M_DIV_W::new(self, 4)
174 }
175 #[doc = "Bit 6 - Set this bit to disable CK8M and CK8M_D256_OUT."]
176 #[inline(always)]
177 pub fn enb_ck8m(&mut self) -> ENB_CK8M_W<CLK_CONF_SPEC> {
178 ENB_CK8M_W::new(self, 6)
179 }
180 #[doc = "Bit 7 - Selects the CK8M_D256_OUT. 1: CK8M 0: CK8M divided by 256."]
181 #[inline(always)]
182 pub fn enb_ck8m_div(&mut self) -> ENB_CK8M_DIV_W<CLK_CONF_SPEC> {
183 ENB_CK8M_DIV_W::new(self, 7)
184 }
185 #[doc = "Bit 8 - Set this bit to enable CK_XTAL_32K clock for the digital core."]
186 #[inline(always)]
187 pub fn dig_xtal32k_en(&mut self) -> DIG_XTAL32K_EN_W<CLK_CONF_SPEC> {
188 DIG_XTAL32K_EN_W::new(self, 8)
189 }
190 #[doc = "Bit 9 - Set this bit to enable CK8M_D256_OUT clock for the digital core."]
191 #[inline(always)]
192 pub fn dig_clk8m_d256_en(&mut self) -> DIG_CLK8M_D256_EN_W<CLK_CONF_SPEC> {
193 DIG_CLK8M_D256_EN_W::new(self, 9)
194 }
195 #[doc = "Bit 10 - Set this bit to enable 8 MHz clock for the digital core."]
196 #[inline(always)]
197 pub fn dig_clk8m_en(&mut self) -> DIG_CLK8M_EN_W<CLK_CONF_SPEC> {
198 DIG_CLK8M_EN_W::new(self, 10)
199 }
200 #[doc = "Bits 12:14 - Stores the 8 MHz divider, which is reg_ck8m_div_sel + 1"]
201 #[inline(always)]
202 pub fn ck8m_div_sel(&mut self) -> CK8M_DIV_SEL_W<CLK_CONF_SPEC> {
203 CK8M_DIV_SEL_W::new(self, 12)
204 }
205 #[doc = "Bit 15 - Set this bit to force no gating to crystal during sleep"]
206 #[inline(always)]
207 pub fn xtal_force_nogating(&mut self) -> XTAL_FORCE_NOGATING_W<CLK_CONF_SPEC> {
208 XTAL_FORCE_NOGATING_W::new(self, 15)
209 }
210 #[doc = "Bit 16 - Set this bit to disable force gating to 8 MHz crystal during sleep."]
211 #[inline(always)]
212 pub fn ck8m_force_nogating(&mut self) -> CK8M_FORCE_NOGATING_W<CLK_CONF_SPEC> {
213 CK8M_FORCE_NOGATING_W::new(self, 16)
214 }
215 #[doc = "Bits 17:24 - CK8M_DFREQ"]
216 #[inline(always)]
217 pub fn ck8m_dfreq(&mut self) -> CK8M_DFREQ_W<CLK_CONF_SPEC> {
218 CK8M_DFREQ_W::new(self, 17)
219 }
220 #[doc = "Bit 25 - Set this bit to FPD the 8 MHz clock."]
221 #[inline(always)]
222 pub fn ck8m_force_pd(&mut self) -> CK8M_FORCE_PD_W<CLK_CONF_SPEC> {
223 CK8M_FORCE_PD_W::new(self, 25)
224 }
225 #[doc = "Bit 26 - Set this bit to FPU the 8 MHz clock."]
226 #[inline(always)]
227 pub fn ck8m_force_pu(&mut self) -> CK8M_FORCE_PU_W<CLK_CONF_SPEC> {
228 CK8M_FORCE_PU_W::new(self, 26)
229 }
230 #[doc = "Bit 29 - Set this bit to select the RTC fast clock. 0: XTAL div 4, 1: CK8M."]
231 #[inline(always)]
232 pub fn fast_clk_rtc_sel(&mut self) -> FAST_CLK_RTC_SEL_W<CLK_CONF_SPEC> {
233 FAST_CLK_RTC_SEL_W::new(self, 29)
234 }
235 #[doc = "Bits 30:31 - Set this bit to select the RTC slow clock. 0: 90K rtc_clk 1: 32k XTAL 2: 8md256."]
236 #[inline(always)]
237 pub fn ana_clk_rtc_sel(&mut self) -> ANA_CLK_RTC_SEL_W<CLK_CONF_SPEC> {
238 ANA_CLK_RTC_SEL_W::new(self, 30)
239 }
240}
241#[doc = "RTC clock configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`clk_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
242pub struct CLK_CONF_SPEC;
243impl crate::RegisterSpec for CLK_CONF_SPEC {
244 type Ux = u32;
245}
246#[doc = "`read()` method returns [`clk_conf::R`](R) reader structure"]
247impl crate::Readable for CLK_CONF_SPEC {}
248#[doc = "`write(|w| ..)` method takes [`clk_conf::W`](W) writer structure"]
249impl crate::Writable for CLK_CONF_SPEC {
250 type Safety = crate::Unsafe;
251}
252#[doc = "`reset()` method sets CLK_CONF to value 0x0158_3218"]
253impl crate::Resettable for CLK_CONF_SPEC {
254 const RESET_VALUE: u32 = 0x0158_3218;
255}