1#[doc = "Register `INT_ST` reader"]
2pub type R = crate::R<INT_ST_SPEC>;
3#[doc = "Field `CH_TX_END(0-3)` reader - The masked interrupt status bit for CH%s_TX_END_INT."]
4pub type CH_TX_END_R = crate::BitReader;
5#[doc = "Field `CH_RX_END(0-3)` reader - The masked interrupt status bit for CH%s_RX_END_INT."]
6pub type CH_RX_END_R = crate::BitReader;
7#[doc = "Field `CH_ERR(0-3)` reader - The masked interrupt status bit for CH%s_ERR_INT."]
8pub type CH_ERR_R = crate::BitReader;
9#[doc = "Field `CH_TX_THR_EVENT(0-3)` reader - The masked interrupt status bit for CH%s_TX_THR_EVENT_INT."]
10pub type CH_TX_THR_EVENT_R = crate::BitReader;
11#[doc = "Field `CH_TX_LOOP(0-3)` reader - The masked interrupt status bit for CH%s_TX_LOOP_INT."]
12pub type CH_TX_LOOP_R = crate::BitReader;
13impl R {
14 #[doc = "The masked interrupt status bit for CH(0-3)_TX_END_INT."]
15 #[doc = ""]
16 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_TX_END` field.</div>"]
17 #[inline(always)]
18 pub fn ch_tx_end(&self, n: u8) -> CH_TX_END_R {
19 #[allow(clippy::no_effect)]
20 [(); 4][n as usize];
21 CH_TX_END_R::new(((self.bits >> (n * 3)) & 1) != 0)
22 }
23 #[doc = "Iterator for array of:"]
24 #[doc = "The masked interrupt status bit for CH(0-3)_TX_END_INT."]
25 #[inline(always)]
26 pub fn ch_tx_end_iter(&self) -> impl Iterator<Item = CH_TX_END_R> + '_ {
27 (0..4).map(move |n| CH_TX_END_R::new(((self.bits >> (n * 3)) & 1) != 0))
28 }
29 #[doc = "Bit 0 - The masked interrupt status bit for CH0_TX_END_INT."]
30 #[inline(always)]
31 pub fn ch0_tx_end(&self) -> CH_TX_END_R {
32 CH_TX_END_R::new((self.bits & 1) != 0)
33 }
34 #[doc = "Bit 3 - The masked interrupt status bit for CH1_TX_END_INT."]
35 #[inline(always)]
36 pub fn ch1_tx_end(&self) -> CH_TX_END_R {
37 CH_TX_END_R::new(((self.bits >> 3) & 1) != 0)
38 }
39 #[doc = "Bit 6 - The masked interrupt status bit for CH2_TX_END_INT."]
40 #[inline(always)]
41 pub fn ch2_tx_end(&self) -> CH_TX_END_R {
42 CH_TX_END_R::new(((self.bits >> 6) & 1) != 0)
43 }
44 #[doc = "Bit 9 - The masked interrupt status bit for CH3_TX_END_INT."]
45 #[inline(always)]
46 pub fn ch3_tx_end(&self) -> CH_TX_END_R {
47 CH_TX_END_R::new(((self.bits >> 9) & 1) != 0)
48 }
49 #[doc = "The masked interrupt status bit for CH(0-3)_RX_END_INT."]
50 #[doc = ""]
51 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_RX_END` field.</div>"]
52 #[inline(always)]
53 pub fn ch_rx_end(&self, n: u8) -> CH_RX_END_R {
54 #[allow(clippy::no_effect)]
55 [(); 4][n as usize];
56 CH_RX_END_R::new(((self.bits >> (n * 3 + 1)) & 1) != 0)
57 }
58 #[doc = "Iterator for array of:"]
59 #[doc = "The masked interrupt status bit for CH(0-3)_RX_END_INT."]
60 #[inline(always)]
61 pub fn ch_rx_end_iter(&self) -> impl Iterator<Item = CH_RX_END_R> + '_ {
62 (0..4).map(move |n| CH_RX_END_R::new(((self.bits >> (n * 3 + 1)) & 1) != 0))
63 }
64 #[doc = "Bit 1 - The masked interrupt status bit for CH0_RX_END_INT."]
65 #[inline(always)]
66 pub fn ch0_rx_end(&self) -> CH_RX_END_R {
67 CH_RX_END_R::new(((self.bits >> 1) & 1) != 0)
68 }
69 #[doc = "Bit 4 - The masked interrupt status bit for CH1_RX_END_INT."]
70 #[inline(always)]
71 pub fn ch1_rx_end(&self) -> CH_RX_END_R {
72 CH_RX_END_R::new(((self.bits >> 4) & 1) != 0)
73 }
74 #[doc = "Bit 7 - The masked interrupt status bit for CH2_RX_END_INT."]
75 #[inline(always)]
76 pub fn ch2_rx_end(&self) -> CH_RX_END_R {
77 CH_RX_END_R::new(((self.bits >> 7) & 1) != 0)
78 }
79 #[doc = "Bit 10 - The masked interrupt status bit for CH3_RX_END_INT."]
80 #[inline(always)]
81 pub fn ch3_rx_end(&self) -> CH_RX_END_R {
82 CH_RX_END_R::new(((self.bits >> 10) & 1) != 0)
83 }
84 #[doc = "The masked interrupt status bit for CH(0-3)_ERR_INT."]
85 #[doc = ""]
86 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_ERR` field.</div>"]
87 #[inline(always)]
88 pub fn ch_err(&self, n: u8) -> CH_ERR_R {
89 #[allow(clippy::no_effect)]
90 [(); 4][n as usize];
91 CH_ERR_R::new(((self.bits >> (n * 3 + 2)) & 1) != 0)
92 }
93 #[doc = "Iterator for array of:"]
94 #[doc = "The masked interrupt status bit for CH(0-3)_ERR_INT."]
95 #[inline(always)]
96 pub fn ch_err_iter(&self) -> impl Iterator<Item = CH_ERR_R> + '_ {
97 (0..4).map(move |n| CH_ERR_R::new(((self.bits >> (n * 3 + 2)) & 1) != 0))
98 }
99 #[doc = "Bit 2 - The masked interrupt status bit for CH0_ERR_INT."]
100 #[inline(always)]
101 pub fn ch0_err(&self) -> CH_ERR_R {
102 CH_ERR_R::new(((self.bits >> 2) & 1) != 0)
103 }
104 #[doc = "Bit 5 - The masked interrupt status bit for CH1_ERR_INT."]
105 #[inline(always)]
106 pub fn ch1_err(&self) -> CH_ERR_R {
107 CH_ERR_R::new(((self.bits >> 5) & 1) != 0)
108 }
109 #[doc = "Bit 8 - The masked interrupt status bit for CH2_ERR_INT."]
110 #[inline(always)]
111 pub fn ch2_err(&self) -> CH_ERR_R {
112 CH_ERR_R::new(((self.bits >> 8) & 1) != 0)
113 }
114 #[doc = "Bit 11 - The masked interrupt status bit for CH3_ERR_INT."]
115 #[inline(always)]
116 pub fn ch3_err(&self) -> CH_ERR_R {
117 CH_ERR_R::new(((self.bits >> 11) & 1) != 0)
118 }
119 #[doc = "The masked interrupt status bit for CH(0-3)_TX_THR_EVENT_INT."]
120 #[doc = ""]
121 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_TX_THR_EVENT` field.</div>"]
122 #[inline(always)]
123 pub fn ch_tx_thr_event(&self, n: u8) -> CH_TX_THR_EVENT_R {
124 #[allow(clippy::no_effect)]
125 [(); 4][n as usize];
126 CH_TX_THR_EVENT_R::new(((self.bits >> (n + 12)) & 1) != 0)
127 }
128 #[doc = "Iterator for array of:"]
129 #[doc = "The masked interrupt status bit for CH(0-3)_TX_THR_EVENT_INT."]
130 #[inline(always)]
131 pub fn ch_tx_thr_event_iter(&self) -> impl Iterator<Item = CH_TX_THR_EVENT_R> + '_ {
132 (0..4).map(move |n| CH_TX_THR_EVENT_R::new(((self.bits >> (n + 12)) & 1) != 0))
133 }
134 #[doc = "Bit 12 - The masked interrupt status bit for CH0_TX_THR_EVENT_INT."]
135 #[inline(always)]
136 pub fn ch0_tx_thr_event(&self) -> CH_TX_THR_EVENT_R {
137 CH_TX_THR_EVENT_R::new(((self.bits >> 12) & 1) != 0)
138 }
139 #[doc = "Bit 13 - The masked interrupt status bit for CH1_TX_THR_EVENT_INT."]
140 #[inline(always)]
141 pub fn ch1_tx_thr_event(&self) -> CH_TX_THR_EVENT_R {
142 CH_TX_THR_EVENT_R::new(((self.bits >> 13) & 1) != 0)
143 }
144 #[doc = "Bit 14 - The masked interrupt status bit for CH2_TX_THR_EVENT_INT."]
145 #[inline(always)]
146 pub fn ch2_tx_thr_event(&self) -> CH_TX_THR_EVENT_R {
147 CH_TX_THR_EVENT_R::new(((self.bits >> 14) & 1) != 0)
148 }
149 #[doc = "Bit 15 - The masked interrupt status bit for CH3_TX_THR_EVENT_INT."]
150 #[inline(always)]
151 pub fn ch3_tx_thr_event(&self) -> CH_TX_THR_EVENT_R {
152 CH_TX_THR_EVENT_R::new(((self.bits >> 15) & 1) != 0)
153 }
154 #[doc = "The masked interrupt status bit for CH(0-3)_TX_LOOP_INT."]
155 #[doc = ""]
156 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_TX_LOOP` field.</div>"]
157 #[inline(always)]
158 pub fn ch_tx_loop(&self, n: u8) -> CH_TX_LOOP_R {
159 #[allow(clippy::no_effect)]
160 [(); 4][n as usize];
161 CH_TX_LOOP_R::new(((self.bits >> (n + 16)) & 1) != 0)
162 }
163 #[doc = "Iterator for array of:"]
164 #[doc = "The masked interrupt status bit for CH(0-3)_TX_LOOP_INT."]
165 #[inline(always)]
166 pub fn ch_tx_loop_iter(&self) -> impl Iterator<Item = CH_TX_LOOP_R> + '_ {
167 (0..4).map(move |n| CH_TX_LOOP_R::new(((self.bits >> (n + 16)) & 1) != 0))
168 }
169 #[doc = "Bit 16 - The masked interrupt status bit for CH0_TX_LOOP_INT."]
170 #[inline(always)]
171 pub fn ch0_tx_loop(&self) -> CH_TX_LOOP_R {
172 CH_TX_LOOP_R::new(((self.bits >> 16) & 1) != 0)
173 }
174 #[doc = "Bit 17 - The masked interrupt status bit for CH1_TX_LOOP_INT."]
175 #[inline(always)]
176 pub fn ch1_tx_loop(&self) -> CH_TX_LOOP_R {
177 CH_TX_LOOP_R::new(((self.bits >> 17) & 1) != 0)
178 }
179 #[doc = "Bit 18 - The masked interrupt status bit for CH2_TX_LOOP_INT."]
180 #[inline(always)]
181 pub fn ch2_tx_loop(&self) -> CH_TX_LOOP_R {
182 CH_TX_LOOP_R::new(((self.bits >> 18) & 1) != 0)
183 }
184 #[doc = "Bit 19 - The masked interrupt status bit for CH3_TX_LOOP_INT."]
185 #[inline(always)]
186 pub fn ch3_tx_loop(&self) -> CH_TX_LOOP_R {
187 CH_TX_LOOP_R::new(((self.bits >> 19) & 1) != 0)
188 }
189}
190#[cfg(feature = "impl-register-debug")]
191impl core::fmt::Debug for R {
192 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
193 f.debug_struct("INT_ST")
194 .field("ch0_tx_end", &self.ch0_tx_end())
195 .field("ch1_tx_end", &self.ch1_tx_end())
196 .field("ch2_tx_end", &self.ch2_tx_end())
197 .field("ch3_tx_end", &self.ch3_tx_end())
198 .field("ch0_rx_end", &self.ch0_rx_end())
199 .field("ch1_rx_end", &self.ch1_rx_end())
200 .field("ch2_rx_end", &self.ch2_rx_end())
201 .field("ch3_rx_end", &self.ch3_rx_end())
202 .field("ch0_err", &self.ch0_err())
203 .field("ch1_err", &self.ch1_err())
204 .field("ch2_err", &self.ch2_err())
205 .field("ch3_err", &self.ch3_err())
206 .field("ch0_tx_thr_event", &self.ch0_tx_thr_event())
207 .field("ch1_tx_thr_event", &self.ch1_tx_thr_event())
208 .field("ch2_tx_thr_event", &self.ch2_tx_thr_event())
209 .field("ch3_tx_thr_event", &self.ch3_tx_thr_event())
210 .field("ch0_tx_loop", &self.ch0_tx_loop())
211 .field("ch1_tx_loop", &self.ch1_tx_loop())
212 .field("ch2_tx_loop", &self.ch2_tx_loop())
213 .field("ch3_tx_loop", &self.ch3_tx_loop())
214 .finish()
215 }
216}
217#[doc = "Masked interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
218pub struct INT_ST_SPEC;
219impl crate::RegisterSpec for INT_ST_SPEC {
220 type Ux = u32;
221}
222#[doc = "`read()` method returns [`int_st::R`](R) reader structure"]
223impl crate::Readable for INT_ST_SPEC {}
224#[doc = "`reset()` method sets INT_ST to value 0"]
225impl crate::Resettable for INT_ST_SPEC {}