esp32s2/apb_saradc/
ctrl2.rs1#[doc = "Register `CTRL2` reader"]
2pub type R = crate::R<CTRL2_SPEC>;
3#[doc = "Register `CTRL2` writer"]
4pub type W = crate::W<CTRL2_SPEC>;
5#[doc = "Field `MEAS_NUM_LIMIT` reader - Enable limit times of SAR ADC sample."]
6pub type MEAS_NUM_LIMIT_R = crate::BitReader;
7#[doc = "Field `MEAS_NUM_LIMIT` writer - Enable limit times of SAR ADC sample."]
8pub type MEAS_NUM_LIMIT_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `MAX_MEAS_NUM` reader - Set maximum conversion number."]
10pub type MAX_MEAS_NUM_R = crate::FieldReader;
11#[doc = "Field `MAX_MEAS_NUM` writer - Set maximum conversion number."]
12pub type MAX_MEAS_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
13#[doc = "Field `SAR1_INV` reader - 1: data to DIG ADC1 CTRL is inverted, otherwise not."]
14pub type SAR1_INV_R = crate::BitReader;
15#[doc = "Field `SAR1_INV` writer - 1: data to DIG ADC1 CTRL is inverted, otherwise not."]
16pub type SAR1_INV_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `SAR2_INV` reader - 1: data to DIG ADC2 CTRL is inverted, otherwise not."]
18pub type SAR2_INV_R = crate::BitReader;
19#[doc = "Field `SAR2_INV` writer - 1: data to DIG ADC2 CTRL is inverted, otherwise not."]
20pub type SAR2_INV_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `TIMER_SEL` reader - 1: select saradc timer 0: i2s_ws trigger"]
22pub type TIMER_SEL_R = crate::BitReader;
23#[doc = "Field `TIMER_SEL` writer - 1: select saradc timer 0: i2s_ws trigger"]
24pub type TIMER_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `TIMER_TARGET` reader - Set SAR ADC timer target."]
26pub type TIMER_TARGET_R = crate::FieldReader<u16>;
27#[doc = "Field `TIMER_TARGET` writer - Set SAR ADC timer target."]
28pub type TIMER_TARGET_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
29#[doc = "Field `TIMER_EN` reader - Enable SAR ADC timer trigger."]
30pub type TIMER_EN_R = crate::BitReader;
31#[doc = "Field `TIMER_EN` writer - Enable SAR ADC timer trigger."]
32pub type TIMER_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
33impl R {
34 #[doc = "Bit 0 - Enable limit times of SAR ADC sample."]
35 #[inline(always)]
36 pub fn meas_num_limit(&self) -> MEAS_NUM_LIMIT_R {
37 MEAS_NUM_LIMIT_R::new((self.bits & 1) != 0)
38 }
39 #[doc = "Bits 1:8 - Set maximum conversion number."]
40 #[inline(always)]
41 pub fn max_meas_num(&self) -> MAX_MEAS_NUM_R {
42 MAX_MEAS_NUM_R::new(((self.bits >> 1) & 0xff) as u8)
43 }
44 #[doc = "Bit 9 - 1: data to DIG ADC1 CTRL is inverted, otherwise not."]
45 #[inline(always)]
46 pub fn sar1_inv(&self) -> SAR1_INV_R {
47 SAR1_INV_R::new(((self.bits >> 9) & 1) != 0)
48 }
49 #[doc = "Bit 10 - 1: data to DIG ADC2 CTRL is inverted, otherwise not."]
50 #[inline(always)]
51 pub fn sar2_inv(&self) -> SAR2_INV_R {
52 SAR2_INV_R::new(((self.bits >> 10) & 1) != 0)
53 }
54 #[doc = "Bit 11 - 1: select saradc timer 0: i2s_ws trigger"]
55 #[inline(always)]
56 pub fn timer_sel(&self) -> TIMER_SEL_R {
57 TIMER_SEL_R::new(((self.bits >> 11) & 1) != 0)
58 }
59 #[doc = "Bits 12:23 - Set SAR ADC timer target."]
60 #[inline(always)]
61 pub fn timer_target(&self) -> TIMER_TARGET_R {
62 TIMER_TARGET_R::new(((self.bits >> 12) & 0x0fff) as u16)
63 }
64 #[doc = "Bit 24 - Enable SAR ADC timer trigger."]
65 #[inline(always)]
66 pub fn timer_en(&self) -> TIMER_EN_R {
67 TIMER_EN_R::new(((self.bits >> 24) & 1) != 0)
68 }
69}
70#[cfg(feature = "impl-register-debug")]
71impl core::fmt::Debug for R {
72 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
73 f.debug_struct("CTRL2")
74 .field("meas_num_limit", &self.meas_num_limit())
75 .field("max_meas_num", &self.max_meas_num())
76 .field("sar1_inv", &self.sar1_inv())
77 .field("sar2_inv", &self.sar2_inv())
78 .field("timer_sel", &self.timer_sel())
79 .field("timer_target", &self.timer_target())
80 .field("timer_en", &self.timer_en())
81 .finish()
82 }
83}
84impl W {
85 #[doc = "Bit 0 - Enable limit times of SAR ADC sample."]
86 #[inline(always)]
87 pub fn meas_num_limit(&mut self) -> MEAS_NUM_LIMIT_W<CTRL2_SPEC> {
88 MEAS_NUM_LIMIT_W::new(self, 0)
89 }
90 #[doc = "Bits 1:8 - Set maximum conversion number."]
91 #[inline(always)]
92 pub fn max_meas_num(&mut self) -> MAX_MEAS_NUM_W<CTRL2_SPEC> {
93 MAX_MEAS_NUM_W::new(self, 1)
94 }
95 #[doc = "Bit 9 - 1: data to DIG ADC1 CTRL is inverted, otherwise not."]
96 #[inline(always)]
97 pub fn sar1_inv(&mut self) -> SAR1_INV_W<CTRL2_SPEC> {
98 SAR1_INV_W::new(self, 9)
99 }
100 #[doc = "Bit 10 - 1: data to DIG ADC2 CTRL is inverted, otherwise not."]
101 #[inline(always)]
102 pub fn sar2_inv(&mut self) -> SAR2_INV_W<CTRL2_SPEC> {
103 SAR2_INV_W::new(self, 10)
104 }
105 #[doc = "Bit 11 - 1: select saradc timer 0: i2s_ws trigger"]
106 #[inline(always)]
107 pub fn timer_sel(&mut self) -> TIMER_SEL_W<CTRL2_SPEC> {
108 TIMER_SEL_W::new(self, 11)
109 }
110 #[doc = "Bits 12:23 - Set SAR ADC timer target."]
111 #[inline(always)]
112 pub fn timer_target(&mut self) -> TIMER_TARGET_W<CTRL2_SPEC> {
113 TIMER_TARGET_W::new(self, 12)
114 }
115 #[doc = "Bit 24 - Enable SAR ADC timer trigger."]
116 #[inline(always)]
117 pub fn timer_en(&mut self) -> TIMER_EN_W<CTRL2_SPEC> {
118 TIMER_EN_W::new(self, 24)
119 }
120}
121#[doc = "DIG ADC common configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
122pub struct CTRL2_SPEC;
123impl crate::RegisterSpec for CTRL2_SPEC {
124 type Ux = u32;
125}
126#[doc = "`read()` method returns [`ctrl2::R`](R) reader structure"]
127impl crate::Readable for CTRL2_SPEC {}
128#[doc = "`write(|w| ..)` method takes [`ctrl2::W`](W) writer structure"]
129impl crate::Writable for CTRL2_SPEC {
130 type Safety = crate::Unsafe;
131}
132#[doc = "`reset()` method sets CTRL2 to value 0xa1fe"]
133impl crate::Resettable for CTRL2_SPEC {
134 const RESET_VALUE: u32 = 0xa1fe;
135}