Type Alias R

pub type R = R<CONF0_SPEC>;

Register CONF0 reader

Aliased Type

pub struct R { /* private fields */ }

Implementations

impl R

pub fn parity(&self) -> PARITY_R

Bit 0 - This register is used to configure the parity check mode. 0: even. 1: odd.

pub fn parity_en(&self) -> PARITY_EN_R

Bit 1 - Set this bit to enable UART parity check.

pub fn bit_num(&self) -> BIT_NUM_R

Bits 2:3 - This register is used to set the length of data. 0: 5 bits. 1: 6 bits. 2: 7 bits. 3: 8 bits.

pub fn stop_bit_num(&self) -> STOP_BIT_NUM_R

Bits 4:5 - This register is used to set the length of stop bit. 1: 1 bit. 2: 1.5 bits. 3: 2 bits.

pub fn sw_rts(&self) -> SW_RTS_R

Bit 6 - This register is used to configure the software RTS signal which is used in software flow control.

pub fn sw_dtr(&self) -> SW_DTR_R

Bit 7 - This register is used to configure the software DTR signal which is used in software flow control.

pub fn txd_brk(&self) -> TXD_BRK_R

Bit 8 - Set this bit to enable the transmitter to send NULL characters when the process of sending data is done.

pub fn irda_dplx(&self) -> IRDA_DPLX_R

Bit 9 - Set this bit to enable IrDA loopback mode.

pub fn irda_tx_en(&self) -> IRDA_TX_EN_R

Bit 10 - This is the start enable bit for IrDA transmitter.

pub fn irda_wctl(&self) -> IRDA_WCTL_R

Bit 11 - 1: The IrDA transmitter’s 11th bit is the same as 10th bit. 0: Set IrDA transmitter’s 11th bit to 0.

pub fn irda_tx_inv(&self) -> IRDA_TX_INV_R

Bit 12 - Set this bit to invert the level of IrDA transmitter.

pub fn irda_rx_inv(&self) -> IRDA_RX_INV_R

Bit 13 - Set this bit to invert the level of IrDA receiver.

pub fn loopback(&self) -> LOOPBACK_R

Bit 14 - Set this bit to enable UART loopback test mode.

pub fn tx_flow_en(&self) -> TX_FLOW_EN_R

Bit 15 - Set this bit to enable flow control function for the transmitter.

pub fn irda_en(&self) -> IRDA_EN_R

Bit 16 - Set this bit to enable IrDA protocol.

pub fn rxfifo_rst(&self) -> RXFIFO_RST_R

Bit 17 - Set this bit to reset the UART RX FIFO.

pub fn txfifo_rst(&self) -> TXFIFO_RST_R

Bit 18 - Set this bit to reset the UART TX FIFO.

pub fn rxd_inv(&self) -> RXD_INV_R

Bit 19 - Set this bit to invert the level of UART RXD signal.

pub fn cts_inv(&self) -> CTS_INV_R

Bit 20 - Set this bit to invert the level of UART CTS signal.

pub fn dsr_inv(&self) -> DSR_INV_R

Bit 21 - Set this bit to invert the level of UART DSR signal.

pub fn txd_inv(&self) -> TXD_INV_R

Bit 22 - Set this bit to invert the level of UART TXD signal.

pub fn rts_inv(&self) -> RTS_INV_R

Bit 23 - Set this bit to invert the level of UART RTS signal.

pub fn dtr_inv(&self) -> DTR_INV_R

Bit 24 - Set this bit to invert the level of UART DTR signal.

pub fn clk_en(&self) -> CLK_EN_R

Bit 25 - 1: Force clock on for registers. 0: Support clock only when application writes registers.

pub fn err_wr_mask(&self) -> ERR_WR_MASK_R

Bit 26 - 1: The receiver stops storing data into FIFO when data is wrong. 0: The receiver stores the data even if the received data is wrong.

pub fn tick_ref_always_on(&self) -> TICK_REF_ALWAYS_ON_R

Bit 27 - This register is used to select the clock. 1: APB_CLK. 0: REF_TICK.

pub fn mem_clk_en(&self) -> MEM_CLK_EN_R

Bit 28 - The signal to enable UART RAM clock gating. 1: UART RAM powers on, the data of which can be read and written. 0: UART RAM powers down.